US Patent Application 18232510. VTFET WITH BURIED POWER RAILS simplified abstract

VTFET WITH BURIED POWER RAILS

Organization Name

International Business Machines Corporation

Inventor(s)

Chen Zhang of Santa Clara CA (US)

Ruilong Xie of Niskayuna NY (US)

Heng Wu of Santa Clara CA (US)

Junli Wang of Slingerlands NY (US)

Brent A. Anderson of Jericho VT (US)

VTFET WITH BURIED POWER RAILS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18232510 titled 'VTFET WITH BURIED POWER RAILS

Simplified Explanation

The patent application describes a semiconductor device that includes several components to improve its performance and functionality.

• The device includes a buried power rail, which is a layer that provides power to the device.
• A buried oxide (BOX) layer is formed on top of the buried power rail.
• A plurality of channel fins are formed on the BOX layer. These channel fins help control the flow of electrical current in the device.
• A bottom epitaxial layer is formed on the BOX layer and between the channel fins. This layer is electrically connected to the buried power rail.
• A gate stack is formed over the bottom epitaxial layer and contacts the channel fins. The gate stack includes a work function metal (WFM) layer and a high-x layer, which help control the flow of electrical current through the device.
• A top epitaxial layer is formed on top of the gate stack.

Overall, this semiconductor device design improves the electrical connectivity and performance of the device by utilizing a buried power rail, a buried oxide layer, and a gate stack with specific layers.

Original Abstract Submitted

A semiconductor device is provided. The semiconductor device includes a buried power rail, a buried oxide (BOX) layer formed on the buried power rail, a plurality of channel fins formed on the BOX layer, a bottom epitaxial layer formed on the BOX layer and between the channel fins such that the BOX layer is between the buried power rail and the bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer and contacting the channel fins, the gate stack including a work function metal (WFM) layer and a high-x layer, and a top epitaxial layer formed on the gate stack. In the semiconductor device, between two adjacent ones of the channel fins the BOX layer has an opening so that the bottom epitaxial layer is electrically connected to the buried power rail.