US Patent Application 17664712. METHOD AND STRUCTURE FOR FORMING LOW CONTACT RESISTANCE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR simplified abstract

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METHOD AND STRUCTURE FOR FORMING LOW CONTACT RESISTANCE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

Organization Name

International Business Machines Corporation

Inventor(s)

Ruilong Xie of Niskayuna NY (US)

Julien Frougier of Albany NY (US)

Andrew M. Greene of Slingerlands NY (US)

REINALDO Vega of Mahopac NY (US)

METHOD AND STRUCTURE FOR FORMING LOW CONTACT RESISTANCE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR - A simplified explanation of the abstract

This abstract first appeared for US patent application 17664712 titled 'METHOD AND STRUCTURE FOR FORMING LOW CONTACT RESISTANCE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

Simplified Explanation

The abstract describes a CMOS device that includes a pFET epi and an nFET epi.

  • The pFET epi has a single dielectric layer that wraps around a portion of the pFET epi and a confined trench epi on another portion of the pFET epi adjacent to a first contact.
  • The nFET epi has a bi-layer dielectric liner that wraps around a portion of the nFET epi and another portion of the nFET epi adjacent to a second contact.


Original Abstract Submitted

A complementary metal oxide semiconductor (CMOS) device. The device includes a pFET epi and an nFET epi. The pFET epi includes a single dielectric layer that wraps around a first portion of the pFET epi and a confined trench epi on a second portion of the pFET epi that is adjacent a first contact. The nFET epi includes a bi-layer dielectric liner that wraps around a first portion of the nFET epi and a second portion of the nFET epi that is adjacent a second contact.

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