PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE HYBRID BONDING

Organization Name

intel corporation

Inventor(s)

Omkar G. Karhade of Chandler AZ US

Harini Kilambi of Portland OR US

Kimin Jun of Portland OR US

Adel A. Elsherbini of Chandler AZ US

John Edward Zeug Matthiesen of Hillsboro OR US

Trianggono Widodo of Hillsboro OR US

Adita Das of Beaverton OR US

Mohit Bhatia of Chandler AZ US

Dimitrios Antartis of Hillsboro OR US

Bhaskar Jyoti Krishnatreya of Hillsboro OR US

Rajesh Surapaneni of Portland OR US

Xavier Francois Brun of Hillsboro OR US

PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE HYBRID BONDING

This abstract first appeared for US patent application 20250006678 titled 'PACKAGING ARCHITECTURE FOR WAFER-SCALE KNOWN-GOOD-DIE HYBRID BONDING

Original Abstract Submitted

disclosed herein are microelectronic assemblies, related apparatuses, and methods. in some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. in some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.