Category:Tao Chu of Portland OR (US)
Tao Chu of Portland OR (US)
Executive Summary
Tao Chu of Portland OR (US) is an inventor who has filed 8 patents. Their primary areas of innovation include No explanation available (4 patents), No explanation available (3 patents), No explanation available (3 patents), and they have worked with companies such as Intel Corporation (8 patents). Their most frequent collaborators include (6 collaborations), (6 collaborations), (6 collaborations).
Patent Filing Activity
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Technology Areas
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List of Technology Areas
- H10D30/6735 (No explanation available): 4 patents
- H10D30/6757 (No explanation available): 3 patents
- H10D62/121 (No explanation available): 3 patents
- H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H10D30/43 (No explanation available): 2 patents
- H10D30/014 (No explanation available): 2 patents
- H01L23/3171 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L21/02532 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L21/823437 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
- H01L21/823475 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
- H01L27/0207 ({Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique}): 1 patents
- H01L27/0886 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L29/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L29/41791 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L29/0673 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L29/1037 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L29/42392 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L29/775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L29/7845 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L29/7851 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/5283 ({Geometry or} layout of the interconnection structure {(): 1 patents
- H10D62/83 (No explanation available): 1 patents
- H01L21/28518 (from a gas or vapour, e.g. condensation): 1 patents
- H01L23/53266 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H10D64/01 (No explanation available): 1 patents
- H10D64/62 (No explanation available): 1 patents
- H01L21/76232 (Dielectric regions {, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers}): 1 patents
- H01L21/76898 ({formed through a semiconductor substrate}): 1 patents
- H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 1 patents
- H10D84/83 (No explanation available): 1 patents
- H10D86/00 (No explanation available): 1 patents
- H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/16235 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H10D62/115 (No explanation available): 1 patents
- H10D30/47 (No explanation available): 1 patents
- H10D62/118 (No explanation available): 1 patents
- H10D84/85 (No explanation available): 1 patents
- H10D30/6219 (No explanation available): 1 patents
- H10D64/687 (No explanation available): 1 patents
- H10D64/679 (No explanation available): 1 patents
- H01L21/28123 ({Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects}): 1 patents
- H01L21/7806 ({involving the separation of the active layers from a substrate}): 1 patents
- H10D30/6729 (No explanation available): 1 patents
- H10D64/017 (No explanation available): 1 patents
Companies
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List of Companies
- Intel Corporation: 8 patents
Collaborators
- Guowei Xu of Portland OR (US) (6 collaborations)
- Chiao-Ti Huang of Portland OR (US) (6 collaborations)
- Robin Chao of Portland OR (US) (6 collaborations)
- Ting-Hsiang Hung of Beaverton OR (US) (6 collaborations)
- Yang Zhang of Rio Rancho NM (US) (6 collaborations)
- Feng Zhang of Hillsboro OR (US) (5 collaborations)
- Chia-Ching Lin of Portland OR (US) (5 collaborations)
- Anand Murthy of Portland OR (US) (5 collaborations)
- Minwoo Jang of Portland OR (US) (3 collaborations)
- Conor P. Puls of Portland OR (US) (3 collaborations)
- Avijit Barik of Portland OR (US) (2 collaborations)
- Chung-Hsun Lin of Portland OR (US) (2 collaborations)
- Aurelia Wang of Hillsboro OR (US) (1 collaborations)
- Yanbin Luo of Portland OR (US) (1 collaborations)
- Paul Packan of Hillsboro OR (US) (1 collaborations)
- Feng Zhang of Hillboro OR (US) (1 collaborations)
- Tofizur RAHMAN of Portland OR (US) (1 collaborations)
- Ariana E. Bondoc of Hillsboro OR (US) (1 collaborations)
- Diane Lancaster of Hillsboro OR (US) (1 collaborations)
- Chi-Hing Choi of Portland OR (US) (1 collaborations)
- Derek Keefer of Hillsboro OR (US) (1 collaborations)
- Jaladhi Mehta of Beaverton OR (US) (1 collaborations)
Subcategories
This category has the following 2 subcategories, out of 2 total.
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Pages in category "Tao Chu of Portland OR (US)"
The following 31 pages are in this category, out of 31 total.
1
- 17940194. EPITAXIAL REGIONS EXTENDING BETWEEN INNER GATE SPACERS simplified abstract (Intel Corporation)
- 17940195. BARRIER LAYER FOR DIELECTRIC RECESS MITIGATION simplified abstract (Intel Corporation)
- 17940944. FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS simplified abstract (Intel Corporation)
- 17956188. ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT simplified abstract (Intel Corporation)
- 18072559. INTEGRATED CIRCUIT STRUCTURES WITH SOURCE OR DRAIN CONTACTS HAVING ENHANCED CONTACT AREA simplified abstract (Intel Corporation)
- 18072569. INTEGRATED CIRCUIT STRUCTURE WITH RECESSED TRENCH CONTACT AND DEEP BOUNDARY VIA simplified abstract (Intel Corporation)
- 18092152. TRANSISTOR WITH CHANNEL MATERIAL IN A STACK WITH INSULATOR MATERIAL SUPPORTS simplified abstract (Intel Corporation)
- 18181598. FABRICATION OF NANORIBBON-BASED TRANSISTORS USING PATTERNED FOUNDATION simplified abstract (Intel Corporation)
- 18187782. INTEGRATED CIRCUIT DEVICE WITH PERFORMANCE-ENHANCING LAYOUT simplified abstract (Intel Corporation)
- 18187801. INTEGRATED CIRCUIT DEVICE WITH REDUCED N-P BOUNDARY EFFECT simplified abstract (Intel Corporation)
- 18187965. ROUNDED NANORIBBONS WITH REGROWN CAPS simplified abstract (Intel Corporation)
- 18187990. LONG CHANNEL FIN TRANSISTORS IN NANORIBBON-BASED DEVICES simplified abstract (Intel Corporation)
- 18216476. MITIGATION OF THRESHOLD VOLTAGE SHIFT IN BACKSIDE POWER DELIVERY USING BACKSIDE PASSIVATION LAYER (Intel Corporation)
- 18216493. PERFORMANCE OPTIMIZATION OF TRANSISTORS SHARING CHANNEL STRUCTURES OF VARYING WIDTH (Intel Corporation)
- 18463436. LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES (Intel Corporation)
- 18466246. THROUGH-GATE STRUCTURE WITH AN AIRGAP SPACER IN A SEMICONDUCTOR DEVICE (Intel Corporation)
I
- Intel corporation (20240105718). INTEGRATED CIRCUIT DEVICES WITH PROTECTION LINER BETWEEN DOPED SEMICONDUCTOR REGIONS simplified abstract
- Intel corporation (20240105770). NECKED RIBBON FOR BETTER N WORKFUNCTION FILLING AND DEVICE PERFORMANCE simplified abstract
- Intel corporation (20240113118). ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT simplified abstract
- Intel corporation (20240178101). INTEGRATED CIRCUIT STRUCTURE WITH RECESSED TRENCH CONTACT AND DEEP BOUNDARY VIA simplified abstract
- Intel corporation (20240178273). INTEGRATED CIRCUIT STRUCTURES WITH SOURCE OR DRAIN CONTACTS HAVING ENHANCED CONTACT AREA simplified abstract
- Intel corporation (20240222484). TRANSISTOR WITH CHANNEL MATERIAL IN A STACK WITH INSULATOR MATERIAL SUPPORTS simplified abstract
- Intel corporation (20240290788). METAL GATE FABRICATION FOR NANORIBBON-BASED TRANSISTORS simplified abstract
- Intel corporation (20240290835). NANORIBBON-BASED TRANSISTORS WITH ETCH STOP LAYER TO ASSIST SUBFIN REMOVAL simplified abstract
- Intel corporation (20240304621). FABRICATION OF NANORIBBON-BASED TRANSISTORS USING PATTERNED FOUNDATION simplified abstract
- Intel corporation (20240321859). INTEGRATED CIRCUIT DEVICE WITH PERFORMANCE-ENHANCING LAYOUT simplified abstract
- Intel corporation (20240321887). INTEGRATED CIRCUIT DEVICE WITH REDUCED N-P BOUNDARY EFFECT simplified abstract
- Intel corporation (20240321962). ROUNDED NANORIBBONS WITH REGROWN CAPS simplified abstract
- Intel corporation (20240321987). LONG CHANNEL FIN TRANSISTORS IN NANORIBBON-BASED DEVICES simplified abstract
- Intel corporation (20250087530). LATERAL ETCHING PROCESS TO REMOVE METAL GATE FOOT STRUCTURES
- Intel corporation (20250089310). THROUGH-GATE STRUCTURE WITH AN AIRGAP SPACER IN A SEMICONDUCTOR DEVICE
Categories:
- Guowei Xu of Portland OR (US)
- Chiao-Ti Huang of Portland OR (US)
- Robin Chao of Portland OR (US)
- Ting-Hsiang Hung of Beaverton OR (US)
- Yang Zhang of Rio Rancho NM (US)
- Feng Zhang of Hillsboro OR (US)
- Chia-Ching Lin of Portland OR (US)
- Anand Murthy of Portland OR (US)
- Minwoo Jang of Portland OR (US)
- Conor P. Puls of Portland OR (US)
- Avijit Barik of Portland OR (US)
- Chung-Hsun Lin of Portland OR (US)
- Aurelia Wang of Hillsboro OR (US)
- Yanbin Luo of Portland OR (US)
- Paul Packan of Hillsboro OR (US)
- Feng Zhang of Hillboro OR (US)
- Tofizur RAHMAN of Portland OR (US)
- Ariana E. Bondoc of Hillsboro OR (US)
- Diane Lancaster of Hillsboro OR (US)
- Chi-Hing Choi of Portland OR (US)
- Derek Keefer of Hillsboro OR (US)
- Jaladhi Mehta of Beaverton OR (US)
- Tao Chu of Portland OR (US)
- Inventors
- Inventors filing patents with Intel Corporation