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Intel corporation (20240257294). COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

From WikiPatents

COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

Organization Name

intel corporation

Inventor(s)

Prasoonkumar Surti of Folsom CA US

Narayan Srinivasa of Portland OR US

Feng Chen of Shanghai CN

Joydeep Ray of Folsom CA US

Ben J. Ashbaugh of Folsom CA US

Nicolas C. Galoppo Von Borries of Portland OR US

Eriko Nurvitadhi of Hillsboro OR US

Balaji Vembu of Folsom CA US

Tsung-Han Lin of Campbell CA US

Kamal Sinha of Rancho Cordova CA US

Rajkishore Barik of Santa Clara CA US

Sara S. Baghsorkhi of San Jose CA US

Justin E. Gottschlich of Santa Clara CA US

Altug Koker of El Dorado Hills CA US

Nadathur Rajagopalan Satish of Santa Clara CA US

Farshad Akhbari of Chandler AZ US

Dukhwan Kim of San Jose CA US

Wenyin Fu of Folsom CA US

Travis T. Schluessler of Hillsboro OR US

Josh B. Mastronarde of Sacramento CA US

Linda L. Hurd of Cool CA US

John H. Feit of Folsom CA US

Jeffery S. Boles of Folsom CA US

Adam T. Lake of Portland OR US

Karthik Vaidyanathan of Berkeley CA US

Devan Burke of Portland OR US

Subramaniam Maiyuran of Gold River CA US

Abhishek R. Appu of El Dorado Hills CA US

COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

This abstract first appeared for US patent application 20240257294 titled 'COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

Original Abstract Submitted

embodiments provide mechanisms to facilitate compute operations for deep neural networks. one embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. the plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. the first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

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