20250218963. Die Conductive Vias Embe (Intel)
DIE AND CONDUCTIVE VIAS EMBEDDED IN A SUBSTRATE
Abstract: an apparatus includes a substrate core, which has a first height between a first surface and a second surface opposite the first surface. a die is within the substrate core. the die may include a deep trench capacitor. the die has a second height between a first side of the die and a second side opposite the first side. the first height is greater than the second height. a plurality of conductive vias extend from a plurality of conductive contacts at the first side of the die to the first surface of the substrate core. a material comprising a dielectric is disposed over the die and encapsulates the plurality of conductive vias. in some embodiments, a bond film is in contact with the second side of the die.
Inventor(s): Hiroki Tanaka, Robert May, Bai Nie, Srinivas Pietambaram, Bohan Shan, Gang Duan, Benjamin Duong, Tolga Acikalin, Soham Agarwal, Jeremy Ecton, Kari Hernandez, Brandon Marin, Pratyush Mishra, Pratyasha Mohapatra, Marcel Said
CPC Classification: H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({ takes precedence; manufacture or treatment } ; mountings per se ; {materials }))
Search for rejections for patent application number 20250218963
- Patent Applications
- Intel Corporation
- CPC H01L23/5386
- Hiroki Tanaka of Gilbert AZ US
- Robert May of Chandler AZ US
- Bai Nie of Chandler AZ US
- Srinivas Pietambaram of Chandler AZ US
- Bohan Shan of Chandler AZ US
- Gang Duan of Chandler AZ US
- Benjamin Duong of Phoenix AZ US
- Tolga Acikalin of San Jose CA US
- Soham Agarwal of Chandler AZ US
- Jeremy Ecton of Gilbert AZ US
- Kari Hernandez of Phoenix AZ US
- Brandon Marin of Gilbert AZ US
- Pratyush Mishra of Tempe AZ US
- Pratyasha Mohapatra of Hillsboro OR US
- Marcel Said of Beaverton OR US