20250218961. Methods Apparatus Fac (Intel)
METHODS AND APPARATUS TO FACILITATE SEMICONDUCTOR DEVICE ALIGNMENT IN AN INTEGRATED CIRCUIT PACKAGE
Abstract: an apparatus includes a package substrate comprising a core having a first surface along a first plane and a second surface along a second plane, a semiconductor device disposed within an opening in the core, the semiconductor device having a third surface along a third plane and a fourth surface along a fourth plane, the third plane substantially parallel to the first plane, a first dielectric material disposed on the first surface of the core, the first dielectric material extends into the opening to fill a first gap between a wall of the opening and a lateral surface of the semiconductor device, and a second dielectric material disposed on the second surface of the core, the second dielectric material extends into the opening to fill a second gap between the second plane and the fourth plane.
Inventor(s): Tolga Acikalin, Benjamin Duong, Soham Agarwal, Jeremy Ecton, Kari Hernandez, Brandon Christian Marin, Pratyush Mishra, Pratyasha Mohapatra, Srinivas Venkata Ramanuja Pietambaram, Marcel Said
CPC Classification: H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({ takes precedence; manufacture or treatment } ; mountings per se ; {materials }))
Search for rejections for patent application number 20250218961
- Patent Applications
- Intel Corporation
- CPC H01L23/5386
- Tolga Acikalin of San Jose CA US
- Benjamin Duong of Phoenix AZ US
- Soham Agarwal of Chandler AZ US
- Jeremy Ecton of Gilbert AZ US
- Kari Hernandez of Phoenix AZ US
- Brandon Christian Marin of Gilbert AZ US
- Pratyush Mishra of Tempe AZ US
- Pratyasha Mohapatra of Hillsboro OR US
- Srinivas Venkata Ramanuja Pietambaram of Chandler AZ US
- Marcel Said of Beaverton OR US