20250218868. Self-aligned Interconnect Fe (Intel)
SELF-ALIGNED INTERCONNECT FEATURES WITH FLOATING DIELECTRIC STRUCTURE
Abstract: an integrated circuit device includes (i) a first interconnect feature extending within a first dielectric material, and (ii) a second interconnect feature extending within the first dielectric material, and landing on the first interconnect feature. the integrated circuit device further includes a layer having a first section and a second section, wherein the layer includes a second dielectric material that is compositionally different from the first dielectric material. an opening between the first section and the second section is above, and vertically aligned to, the first interconnect feature. the second interconnect feature extends through the opening. in an example, each of the first section and the second section is vertically separated from the first interconnect feature by at least 2 nanometers (nm). in an example, a dielectric constant of the second dielectric material is higher than a dielectric constant of the first dielectric material by at least 5%.
Inventor(s): Sudipto Naskar, Christopher J. Jezewski, Akshit Peer, Ananya Dutta, Jiun-Ruey Chen, Matthew V. Metz, Mauro J. Kobrinsky, Bryce C. Walker, Dominic Esan, Weimin C. Han
CPC Classification: H01L21/76897 ({Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step (self-aligned silicidation on field effect transistors )})
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- Patent Applications
- Intel Corporation
- CPC H01L21/76897
- Sudipto Naskar of Portland OR US
- Christopher J. Jezewski of Portland OR US
- Akshit Peer of Hillboro OR US
- Ananya Dutta of
- Jiun-Ruey Chen of Hillsboro OR US
- Matthew V. Metz of Portland OR US
- Mauro J. Kobrinsky of Portland OR US
- Bryce C. Walker of Canby OR US
- Dominic Esan of Hillsboro OR US
- Weimin C. Han of Portland OR US