REDUCTION OF MIDDLE-OF-LINE RESISTANCE AND CAPACITANCE

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Brent A. Anderson of Jericho VT (US)

Nicholas Anthony Lanzillo of Wynantskill NY (US)

Albert M. Chu of Nashua NH (US)

Ruilong Xie of Niskayuna NY (US)

Lawrence A. Clevenger of Saratoga Springs NY (US)

Reinaldo Vega of Mahopac NY (US)

REDUCTION OF MIDDLE-OF-LINE RESISTANCE AND CAPACITANCE

This abstract first appeared for US patent application 18333863 titled 'REDUCTION OF MIDDLE-OF-LINE RESISTANCE AND CAPACITANCE

Original Abstract Submitted

A semiconductor structure includes a plurality of vertical transport field effect transistors, and an interconnect structure connected to one of respective source/drain regions of at least two vertical transport field effect transistors of the plurality of vertical transport field effect transistors and respective gate regions of the at least two vertical transport field effect transistors. The interconnect structure comprises a damascene portion, and a subtractive portion disposed on the damascene portion.