STACKED LINEAR DOUBLE-LENGTH VTFETS

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Brent A. Anderson of Jericho VT (US)

Ruilong Xie of Niskayuna NY (US)

Albert M. Chu of Nashua NH (US)

Nicholas Anthony Lanzillo of Wynantskill NY (US)

Reinaldo Vega of Mahopac NY (US)

STACKED LINEAR DOUBLE-LENGTH VTFETS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18188042 titled 'STACKED LINEAR DOUBLE-LENGTH VTFETS

The patent application describes semiconductor devices with colinear vertical transfer field effect transistors (VTFETs) in two layers, with shared bottom source/drain structures in each layer.

Lower layer includes colinear first VTFETs with shared bottom source/drain structure
Upper layer includes colinear upper VTFETs with shared bottom source/drain structure
First layer positioned below second layer
First layer includes lower colinear VTFETs
Second layer includes upper colinear VTFETs

Potential Applications: - Semiconductor manufacturing - Electronics industry - Integrated circuits

Problems Solved: - Efficient use of space in semiconductor devices - Enhanced performance of VTFETs - Simplified manufacturing process

Benefits: - Improved device performance - Higher integration density - Cost-effective manufacturing

Commercial Applications: - Production of advanced semiconductor devices - Integration into various electronic devices - Potential for use in consumer electronics, telecommunications, and computing industries

Questions about the technology: 1. How does the shared bottom source/drain structure benefit the overall performance of the semiconductor devices? 2. What are the potential challenges in implementing colinear VTFETs in semiconductor manufacturing processes?

Original Abstract Submitted

Semiconductor devices and methods of forming the same include a first layer including lower colinear vertical transfer field effect transistors (VTFETs). At least two of the colinear first VTFETs have a first shared bottom source/drain structure. A second layer is positioned over the first layer and includes upper colinear VTFETs. At least two of the upper colinear VTFETs have a second shared bottom source/drain structure.