Taiwan Semiconductor Manufacturing Company Limited patent applications published on November 30th, 2023

Patent applications for Taiwan Semiconductor Manufacturing Company Limited on November 30th, 2023

Systems and Methods for Classifying PUF Signature Modules of Integrated Circuits (18446838)

Main Inventor

Cheng-En Lee

Brief explanation

- The patent application describes a method for determining the reliability of a physically unclonable function (PUF) cell in a device.

- The method involves providing activation signals to the PUF cell under different conditions and determining the output of the PUF cell for each condition. - The number of times the PUF cell output is consistent is then determined, indicating its reliability. - Based on the determined number of consistent outputs, a device classification value is determined for a plurality of PUF cells. - The innovation aims to provide a reliable and accurate assessment of the reliability of PUF cells in a device.

Abstract

Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. One or more activation signals are provided to a PUF cell under a plurality of conditions. A PUF cell output provided by the PUF cell under each of the plurality of conditions is determined. A determination is made of a number of times the PUF cell output of the PUF cell is consistent. And a device classification value is determined based on the determined number of times for a plurality of PUF cells.

Mixed Poly Pitch Design Solution for Power Trim (18361948)

Main Inventor

Shih-Wei Peng

Brief explanation

The patent application describes an integrated circuit that has different pitch sizes for its cells.

• The integrated circuit includes a minimum unit that has a certain number of cells with a first pitch size and a different number of cells with a second pitch size.
• The first pitch size and the second pitch size are different from each other, and their greatest common divisor is an integer greater than 1.
• The first pitch size has a gate length of Lg, and the second pitch size has a gate length of Lg1.
• The gate lengths can be extended to achieve G-bias, which optimizes power and speed for the minimum unit and the integrated circuit.

Abstract

An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.

INTEGRATED CHIP PACKAGE INCLUDING A CRACK-RESISTANT LID STRUCTURE AND METHODS OF FORMING THE SAME (17898834)

Main Inventor

Wensen Hung

Brief explanation

The abstract describes a chip package structure that includes an interposer, semiconductor dies, a packaging substrate, and a lid structure.

• The chip package structure consists of an assembly containing an interposer and semiconductor dies.
• A packaging substrate is attached to the assembly using solder material portions.
• A lid structure is attached to the packaging substrate.
• The lid structure includes a first plate portion with a certain thickness located in an interposer-projection region that overlaps with the interposer.
• The lid structure also includes a second plate portion with a smaller thickness surrounding and connected to the first plate portion, but located outside the interposer-projection region.
• Additionally, the lid structure has multiple foot portions connected to the second plate portion, spaced apart from the first plate portion, and attached to the top surface segment of the packaging substrate using adhesive portions.

Abstract

A chip package structure includes an assembly containing an interposer and semiconductor dies; a packaging substrate attached to the assembly through solder material portions; and a lid structure attached to the packaging substrate. The lid structure includes: a first plate portion having a first thickness and located in an interposer-projection region having an areal overlap with the interposer in a plan view; a second plate portion having a second thickness that is less than the first thickness, laterally surrounding, and adjoined to, the first plate portion, and located outside the interposer-projection region; and a plurality of foot portions adjoined to the second plate portion, laterally spaced from the first plate portion, and attached to a respective top surface segment of the packaging substrate through a respective adhesive portion.

PACKAGING SUBSTRATE INCLUDING A STRESS-ABSORPTION TRENCH AND METHODS OF FORMING THE SAME (17828064)

Main Inventor

Hsien-Wei Chen

Brief explanation

The patent application describes a semiconductor structure with a packaging substrate that has a trench between two regions.

• The semiconductor structure includes a packaging substrate with at least one trench located between a first region and a second region.
• A first chip module is bonded to the first region of the packaging substrate using first solder material portions.
• A second chip module is bonded to the second region of the packaging substrate using second solder material portions.
• A first underfill material portion surrounds the first solder material portions and extends into a first portion of the trench.
• A second underfill material portion surrounds the second solder material portions and extends into a second portion of the trench.
• The trench is used to absorb stress to the underfill material portions.

Abstract

A semiconductor structure includes a packaging substrate containing at least one trench located between a first region and a second region, a first chip module bonded to the first region of the packaging substrate through first solder material portions, and a second chip module bonded to the second region of the packaging substrate through second solder material portions. A first underfill material portion laterally surrounds the first solder material portions and extends into a first portion of the at least one trench. A second underfill material portion laterally surrounds the second solder material portions and extends into a second portion of the at least one trench. The at least one trench is used to absorb stress to the underfill material portions.

SEMICONDUCTOR PACKAGE INCLUDING LID WITH INTEGRATED HEAT PIPE FOR THERMAL MANAGEMENT AND METHODS FOR FORMING THE SAME (18366788)

Main Inventor

Yu-Sheng LIN

Brief explanation

- The patent application describes a semiconductor package that includes a lid with one or more heat pipes for improved thermal management.

- The lid is designed to be thermally integrated with the semiconductor package, allowing for more uniform heat loss. - This integration helps reduce the risk of damage to the package caused by excessive heat accumulation. - Additionally, the use of heat pipes in the lid allows for the lid to be made from less expensive materials, leading to cost reduction in the semiconductor package.

Abstract

A semiconductor package including a lid having one or more heat pipes located on and/or within the lid to provide improved thermal management. A lid for a semiconductor package having one or more heat pipes thermally integrated with the lid may provide more uniform heat loss from the semiconductor package, reduce the risk of damage to the package due to excessive heat accumulation, and may enable the lid to be fabricated using less expensive materials, thereby reducing the costs of a semiconductor package.

SEMICONDUCTOR DIE INCLUDING THROUGH SUBSTRATE VIA BARRIER STRUCTURE AND METHODS FOR FORMING THE SAME (18230135)

Main Inventor

Jen-Yuan CHANG

Brief explanation

The patent application describes a die, which is a semiconductor device.

• The die includes a semiconductor substrate with a front side and a back side.
• There is a dielectric structure on the front side of the substrate, consisting of a substrate oxide layer and interlayer dielectric (ILD) layers.
• An interconnect structure is present within the dielectric structure.
• A through-silicon via (TSV) structure extends vertically from the back side of the substrate to the front side, with one end in the interconnect structure.
• A TSV barrier structure is included, which consists of a barrier line that contacts the end of the TSV structure and a seal ring in the substrate oxide layer surrounding the TSV structure horizontally.

Abstract

A die includes: a semiconductor substrate having a front side and an opposing back side; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the back side of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.

REDISTRIBUTION STRUCTURE WITH COPPER BUMPS ON PLANAR METAL INTERCONNECTS AND METHODS OF FORMING THE SAME (17826223)

Main Inventor

Hsien-Wei Chen

Brief explanation

The patent application describes a method for forming redistribution interconnect structures on a carrier wafer, attaching semiconductor dies to these structures, and then exposing the interconnect structures by removing the carrier wafer. Fan-out bump structures are then formed on the exposed surfaces.

• Method for forming redistribution interconnect structures on a carrier wafer
• Semiconductor dies are attached to the redistribution structures
• Carrier wafer and adhesive layer are removed to expose the interconnect structures
• Fan-out bump structures are formed on the exposed surfaces

Abstract

First redistribution interconnect structures having a respective uniform thickness throughout are formed on a top surface of a first adhesive layer over a first carrier wafer. Redistribution dielectric layers and additional redistribution interconnect structures are formed over the first redistribution interconnect structures to provide at least one redistribution structure. A respective set of one or more semiconductor dies is attached to each of the at least one redistribution structure. The first redistribution interconnect structures are physically exposed by removing the first carrier wafer and the first adhesive layer. Fan-out bump structures are formed on the physically exposed first planar surfaces of the first redistribution interconnect structures.

SEMICONDUCTOR PACKAGE WITH VARIABLE PILLAR HEIGHT AND METHODS FOR FORMING THE SAME (17828066)

Main Inventor

Li-Ling Liao

Brief explanation

- The patent application is about semiconductor packages and methods of fabricating them.

- The packages include bonding structures on an interposer, which is a component that connects the semiconductor device to the package substrate. - The interposer has non-uniform height dimensions in different regions, meaning that it is not flat or even throughout. - The non-uniform heights of the interposer compensate for any warping or bending that may occur, improving the reliability of the electrical connections between the interposer and the package substrate. - The electrical connections are made through solder connections that contact pillars on the interposer and connect them to corresponding bonding structures on the package substrate.

Abstract

Semiconductor packages and methods of fabricating semiconductor packages include bonding structures on a surface of an interposer having non-uniform height dimensions in different regions of the interposer. A plurality of solder connections may contact the pillars and electrically connect the respective pillars of the interposer to corresponding bonding structures on a package substrate. The variation in the heights of the pillars in different regions of the interposer may compensate for warping of the interposer and improve the reliability of the electrical connections between the interposer and the package substrate.

DIE CORNER REMOVAL FOR UNDERFILL CRACK SUPPRESSION IN SEMICONDUCTOR DIE PACKAGING (18446554)

Main Inventor

Wei-Yu CHEN

Brief explanation

- The patent application describes a chip package structure that includes a fan-out package, epoxy molding compound (EMC) die frame, and a redistribution structure.

- The fan-out package has chamfer regions that connect horizontal and vertical surfaces via angled surfaces. - The chip package structure may also include a package substrate and an underfill material portion. - The underfill material portion surrounds an array of solder material portions and contacts the angled surfaces. - The angled surfaces help distribute mechanical stress in the chamfer regions and prevent cracks in the underfill material portion.

Abstract

A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.

VERTICAL SEMICONDUCTOR PACKAGE INCLUDING HORIZONTALLY STACKED DIES AND METHODS OF FORMING THE SAME (18230147)

Main Inventor

Jen-Yuan CHANG

Brief explanation

The patent application describes a semiconductor package that includes a first connection die and a first die stack.

• The first connection die has a semiconductor substrate and an interconnect structure.
• The first die stack is placed on top of the first connection die and consists of stacked dies.
• Each stacked die also has a semiconductor substrate and an interconnect structure.
• The interconnect structure of each stacked die is electrically connected to the interconnect structure of the first connection die.
• The angle between the plane of the first connection die and the plane of each stacked die ranges from about 45° to about 90°.

Abstract

A semiconductor package includes a first connection die including a semiconductor substrate and an interconnect structure, and a first die stack disposed on the first connection die and including stacked dies, each of the stacked dies including a semiconductor substrate and an interconnect structure including a first connection line that is electrically connected to the interconnect structure of the first connection die. An angle formed between a plane of the first connection die and a plane of each stacked die ranges from about 45° to about 90°.

Device with a High Efficiency Voltage Multiplier (18447367)

Main Inventor

Yu-Tso Lin

Brief explanation

The patent application describes a device that includes a capacitive element with a transistor, which increases the capacitance without increasing the physical size of the element.

• The device includes a capacitive element that is connected between two nodes.
• The capacitive element consists of a first well region, a second well region, and a transistor.
• The second well region is formed within the first well region and has a different conductivity type.
• The second well region is connected to the second node.
• The transistor includes source and drain regions formed in the second well region and connected to each other and the second node.
• The transistor also includes a channel region between the source and drain regions and a gate region over the channel region.
• The first well region and the gate region are connected to the first node.
• This configuration increases the capacitance of the capacitive element without increasing its physical size.

Abstract

A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

SEMICONDUCTOR ARRANGEMENT WITH ISOLATION STRUCTURE (18232085)

Main Inventor

Feng-Chien HSIEH

Brief explanation

The patent application describes a semiconductor arrangement with a photodiode and isolation structures.

• The photodiode is located in a substrate and extends to a certain depth from one side.
• The isolation structure surrounds the photodiode and includes a well that extends into one side of the substrate.
• A deep trench isolation is present on the other side of the substrate, and part of it is positioned underneath the first well.

Abstract

A semiconductor arrangement includes a photodiode extending to a first depth from a first side in a substrate. An isolation structure laterally surrounds the photodiode and includes a first well that extends into a first side of the substrate. A deep trench isolation extends into a second side of the substrate and at least a portion of the deep trench isolation underlies the first well.

FERROELECTRIC MFM CAPACITOR ARRAY AND METHODS OF MAKING THE SAME (18363217)

Main Inventor

Chun-Chieh LU

Brief explanation

The patent application describes a method for fabricating a specific type of capacitor called an MFM capacitor.

• MFM capacitor has multiple metal contacts and is used in various electronic devices.
• The method involves placing a first metal strip on a substrate in one direction.
• A layer of ferroelectric material is then placed on top of the first metal strip.
• A second metal strip is placed on top of the ferroelectric layer in a different direction.
• Metal contacts are placed between the first and second metal strips in the area where they intersect.
• These metal contacts help in the functioning of the capacitor.
• The invention provides a structure and method for fabricating the MFM capacitor efficiently.

Abstract

Embodiments include structures and methods for fabricating an MFM capacitor having a plurality of metal contacts. An embodiment may include a first metal strip, disposed on a substrate and extending in a first direction, a ferroelectric blanket layer, disposed on the first metal strip, a second metal strip, disposed on the ferroelectric blanket layer and extending in a second direction different from the first direction, and a plurality of metal contacts disposed between the first metal strip and the second metal strip and located within an intersection region of the first metal strip and the second metal strip.

SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING (18231847)

Main Inventor

Shih-Wei PENG

Brief explanation

The patent application describes a method for creating a semiconductor arrangement.

• A first source pad is formed on top of a semiconductor layer.
• A first nanosheet is created, which makes contact with the first source pad.
• A gate pad is placed next to the first nanosheet.
• A first drain pad is formed over the gate pad and also makes contact with the first nanosheet.
• A backside interconnect line is created underneath the gate pad and the first source pad.
• A first backside contact is formed, which makes contact with either the backside interconnect line, the first source pad, or the gate pad.

Abstract

A method of forming a semiconductor arrangement includes forming a first source pad over a semiconductor layer. A first nanosheet is formed contacting the first source pad. A gate pad is formed adjacent the first nanosheet. A first drain pad is formed over the gate pad and contacting the first nanosheet. A backside interconnect line is formed under the gate pad and the first source pad. A first backside contact is formed contacting at least one of the backside interconnect line, the first source pad, or the gate pad.

SELF-ALIGNED ACTIVE REGIONS AND PASSIVATION LAYER AND METHODS OF MAKING THE SAME (18446541)

Main Inventor

Hung Wei LI

Brief explanation

The patent application describes a field effect transistor and a method of making it.

• The field effect transistor consists of active regions, a channel region, and contact via structures.
• The active regions are located over a channel layer, and the channel region is formed within the channel layer between the active regions.
• The contact via structures are electrically connected to the active regions.
• The contact via structures are formed in an interlayer dielectric layer that extends over the channel layer.

Abstract

Field effect transistors and method of making. The field effect transistor includes a pair of active regions over a channel layer, a channel region formed in the channel layer and located between the pair of active regions, and a pair of contact via structures electrically connected to the pair of active regions. The contact via structure is formed in an interlayer dielectric layer that extends over the channel layer.

TRANSISTOR INCLUDING HYDROGEN DIFFUSION BARRIER FILM AND METHODS OF FORMING SAME (18230864)

Main Inventor

Hung Wei LI

Brief explanation

The patent application describes a thin film transistor and a method of making it.

• The thin film transistor includes a substrate, a word line, a semiconductor layer, a hydrogen diffusion barrier layer, a gate dielectric layer, and source and drain electrodes.
• The word line is placed on the substrate.
• The semiconductor layer has a source region, a drain region, and a channel region between them, overlapping with the word line in a vertical direction.
• The hydrogen diffusion barrier layer also overlaps with the channel region in the vertical direction.
• The gate dielectric layer is positioned between the channel region and the word line.
• Source and drain electrodes are connected to the source and drain regions respectively.

Abstract

A thin film transistor and method of making the same, the thin film transistor including: a substrate; a word line disposed on the substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region disposed between the source and drain regions and overlapping with the word line in a vertical direction perpendicular to a plane of the substrate; a hydrogen diffusion barrier layer overlapping with the channel region in the vertical direction; a gate dielectric layer disposed between the channel region and the word line; and source and drain electrodes respectively electrically coupled to the source and drain regions.

RAISED SOURCE/DRAIN OXIDE SEMICONDUCTING THIN FILM TRANSISTOR AND METHODS OF MAKING THE SAME (18366725)

Main Inventor

Gerben Doornbos

Brief explanation

The patent application describes a transistor and methods of making it.

• The transistor has a patterned gate electrode, a dielectric layer, and a patterned first oxide semiconductor layer.
• The first oxide semiconductor layer includes a channel region and source/drain regions.
• The source/drain regions are thicker than the channel region.
• Contacts are located on the first oxide semiconductor layer and connected to the source/drain regions.

Abstract

A transistor, integrated semiconductor device and methods of making are disclosed. The transistor includes a patterned gate electrode, a dielectric layer located over the patterned gate electrode and a patterned first oxide semiconductor layer comprising a channel region and source/drain regions located on sides of the channel region. The thickness of the source/drain regions is greater than a thickness of the channel region. The transistor also includes contacts located on the patterned first oxide semiconductor layer and connected to the source/drain regions of the patterned first oxide semiconductor layer.

Semiconductor Device Including a Layer Between a Source/Drain Region and a Substrate (18366733)

Main Inventor

Kam-Tou Sio

Brief explanation

- The patent application describes devices and methods that eliminate the need for a read assist circuit.

- A semiconductor device is described, which includes a source region and a drain region formed above a substrate. - A buried insulator (BI) layer is formed beneath either the source region or the drain region. - A first nano-sheet is formed horizontally between the source region and the drain region and vertically above the BI layer. - The BI layer reduces current flow through the first nano-sheet.

Abstract

Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.

MOBILITY ENHANCEMENT BY SOURCE AND DRAIN STRESS LAYER OR IMPLANTATION IN THIN FILM TRANSISTORS (18446755)

Main Inventor

Hui-Hsien WEI

Brief explanation

- The patent application describes a method for enhancing the mobility of charge carriers in a semiconducting material layer.

- A planar insulating spacer layer is formed over a substrate. - A combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode is formed over the planar insulating spacer layer. - A dielectric matrix layer is formed above the previous layers. - Source-side and drain-side via cavities are formed through the dielectric matrix layer over the end portions of the semiconducting material layer. - By changing the lattice constant of the end portions of the semiconducting material layer, mechanical stress is generated between them. - This mechanical stress enhances the mobility of charge carriers in the channel portion of the semiconducting material layer.

Abstract

A planar insulating spacer layer can be formed over a substrate, and a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode can be formed over the planar insulating spacer layer. A dielectric matrix layer is formed thereabove. A source-side via cavity and a drain-side via cavity can be formed through the dielectric matrix layer over end portions of the semiconducting material layer. Mechanical stress can be generated between the end portions of the semiconducting material layer by changing a lattice constant of end portions of the semiconducting material layer. The mechanical stress can enhance the mobility of charge carriers in a channel portion of the semiconducting material layer.

MEMORY CHIPLET HAVING MULTIPLE ARRAYS OF MEMORY DEVICES AND METHODS OF FORMING THE SAME (18362192)

Main Inventor

Chao-I WU

Brief explanation

The patent application describes a memory structure that includes three different types of memory arrays: SRAM, 1T1C, and FeFET.

• The memory structure has a data bus that allows for data transfer between the different memory arrays.
• Peripheral circuit devices are included in the memory structure to control the memory arrays.
• The second and third memory arrays may be 3-dimensional, meaning they have multiple layers of memory cells stacked on top of each other.

Abstract

A disclosed memory structure includes a first memory region including a first memory array of SRAM memory devices, a second memory region including a second memory array of 1T1C memory devices, and a third memory region including a third memory array of FeFET memory devices. The memory structure further includes at least one data bus laterally extending across the first memory region, the second memory region, and third memory region and configured to provide data transfer among the first memory array, the second memory array, and the third memory array. The memory structure further includes a plurality of peripheral circuit devices formed at a semiconductor material layer of the memory structure, the peripheral circuit devices configured to control the first memory array, the second memory array, and the third memory array. At least one of the second memory array and the third memory array may be a 3-dimensional memory array.

ENCAPSULATED PHASE CHANGE MATERIAL SWITCH AND METHODS FOR FORMING THE SAME (17826815)

Main Inventor

Tsung-Hsueh Yang

Brief explanation

The patent application describes a method for creating a dielectric isolation layer over a substrate, with electrodes and a phase change material (PCM) line formed on top. A dielectric encapsulation layer is then added to protect the PCM line, and a heater line can be included for additional functionality.

• Dielectric isolation layer formed over a substrate
• First and second electrodes formed on top of the isolation layer
• Insulating matrix layer surrounds the electrodes
• Phase change material (PCM) line placed on top of the insulating matrix layer
• PCM line contacts the top surfaces of the first and second electrodes
• Sidewalls of the PCM line and the insulating matrix layer are covered with a dielectric encapsulation layer
• Heater line is added either underneath or on top of the PCM line
• PCM switch device may be included as part of the overall invention

Abstract

A dielectric isolation layer having a planar top surface is formed over a substrate. A first electrode and a second electrode are formed over the planar top surface. An insulating matrix layer is formed around the first electrode and the second electrode. A phase change material (PCM) line is formed over the insulating matrix layer. A first end portion of the PCM line contacts a top surface of the first electrode and a second end portion of the PCM line contacts a top surface of the second electrode. A dielectric encapsulation layer is formed on sidewalls of the PCM line and over the PCM line and over a top surface of the insulating matrix layer. A heater line is formed prior to, or after, formation of the PCM line. The heater line underlies the PCM line or overlies the PCM line. A PCM switch device may be provided.