US Patent Application 18447367. Device with a High Efficiency Voltage Multiplier simplified abstract
Contents
Device with a High Efficiency Voltage Multiplier
Organization Name
Taiwan Semiconductor Manufacturing Company Limited
Inventor(s)
Yu-Tso Lin of New Taipei City (TW)
Chih-Hsien Chang of New Taipei City (TW)
Robert Bogdan Staszewski of Dublin (IE)
Seyednaser Pourmousavian of Dublin (IE)
Device with a High Efficiency Voltage Multiplier - A simplified explanation of the abstract
This abstract first appeared for US patent application 18447367 titled 'Device with a High Efficiency Voltage Multiplier
Simplified Explanation
The patent application describes a device that includes a capacitive element with a transistor, which increases the capacitance without increasing the physical size of the element.
- The device includes a capacitive element that is connected between two nodes.
- The capacitive element consists of a first well region, a second well region, and a transistor.
- The second well region is formed within the first well region and has a different conductivity type.
- The second well region is connected to the second node.
- The transistor includes source and drain regions formed in the second well region and connected to each other and the second node.
- The transistor also includes a channel region between the source and drain regions and a gate region over the channel region.
- The first well region and the gate region are connected to the first node.
- This configuration increases the capacitance of the capacitive element without increasing its physical size.
Original Abstract Submitted
A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.
