Micron Technology, Inc. patent applications published on February 29th, 2024
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Summary of the patent applications from Micron Technology, Inc. on February 29th, 2024
Micron Technology, Inc. has recently filed patents for innovative memory circuitry designs and methods to enhance the performance and efficiency of semiconductor devices. These patents include integrated assemblies with two different semiconductor materials, memory cells with unique conductive and insulative tiers, and memory arrays with vertically-alternating tiers of memory cells and conductive masses. The designs aim to increase memory storage capacity, improve data processing speeds, and optimize space utilization within electronic devices.
Summary in bullet points:
- Patents focus on memory circuitry designs and methods for semiconductor devices.
- Innovative memory cell arrangements and conductive tiers are key features of the patents.
- Aim to increase memory storage capacity, enhance data processing speeds, and optimize space utilization.
- Designed for various electronic devices and data centers for efficient data storage and retrieval.
Notable applications:
- Memory storage devices
- Computer systems
- Data centers.
Contents
- 1 Patent applications for Micron Technology, Inc. on February 29th, 2024
- 1.1 MULTI-SENSOR TEST DEVICE FOR QUALITY CONTROL SCANNING (17823806)
- 1.2 THERMAL IMPROVEMENTS FOR MEMORY SUB-SYSTEMS (18235169)
- 1.3 MEMORY DEVICE CLOCK MAPPING (17897957)
- 1.4 MEMORY WITH SWITCHABLE CHANNELS (17823909)
- 1.5 MEMORY DEVICE LOG DATA STORAGE (17822250)
- 1.6 ADDRESS TRANSLATION METADATA COMPRESSION IN MEMORY DEVICES (17895696)
- 1.7 VARYING MEMORY ERASE DEPTH ACCORDING TO BLOCK CHARACTERISTICS (18223933)
- 1.8 BALANCING PERFORMANCE BETWEEN INTERFACE PORTS IN A MEMORY SUB-SYSTEM (17900120)
- 1.9 MULTIPLE MEMORY BLOCK ERASE OPERATION (18233433)
- 1.10 UTILIZING LAST SUCCESSFUL READ VOLTAGE LEVEL IN MEMORY ACCESS OPERATIONS (17894540)
- 1.11 MEMORY BLOCK ERASE PROTOCOL (17898333)
- 1.12 ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS (17898160)
- 1.13 EFFECTIVE STORAGE ALLOCATION FOR SEQUENTIALLY-WRITTEN MEMORY DEVICES (18502764)
- 1.14 DYNAMIC WEAR LEVELING TECHNIQUES (17899341)
- 1.15 APPARATUS WITH SIGNAL QUALITY FEEDBACK (17897153)
- 1.16 CROSS-TEMPERATURE COMPENSATION BASED ON MEDIA ENDURANCE IN MEMORY DEVICES (17897784)
- 1.17 REDUCING BIT ERROR RATE IN MEMORY DEVICES (18219023)
- 1.18 ASYMMETRIC PASS THROUGH VOLTAGE FOR REDUCTION OF CELL-TO-CELL INTERFERENCE (18236087)
- 1.19 MEMORY CHIP TEST PAD ACCESS MANAGEMENT TO FACILITATE DATA SECURITY (17946738)
- 1.20 PARTITIONING SYSTEM DATA FROM USER DATA IN MEMORY (17894343)
- 1.21 SHARED MEMORY SNAPSHOTS (17895918)
- 1.22 TRIPLE ACTIVATE COMMAND ROW ADDRESS LATCHING (17899222)
- 1.23 ROW ADDRESS LATCHING FOR MULTIPLE ACTIVATE COMMAND PROTOCOL (17899305)
- 1.24 COMBINED MEMORY MODULE LOGIC DEVICES FOR REDUCED COST AND IMPROVED FUNCTIONALITY (18223249)
- 1.25 SINGLE-BIT ERROR INDICATION FOR A MEMORY BUILT-IN SELF-TEST (17821924)
- 1.26 TWO-TIER DEFECT SCAN MANAGEMENT (17894794)
- 1.27 SELECTIVE DATA MAP UNIT ACCESS (17822606)
- 1.28 HOST-INITIATED AND AUTO-INITIATED NON-VOLATILE MEMORY REFRESH (17897940)
- 1.29 METHOD OF EFFICIENTLY IDENTIFYING ROLLBACK REQUESTS (17823470)
- 1.30 READ OPERATIONS FOR MIXED DATA (17822893)
- 1.31 DEFERRED ZONE ADJUSTMENT IN ZONE MEMORY SYSTEM (17899801)
- 1.32 SUPER BLOCK MANAGEMENT FOR EFFICIENT UTILIZATION (18237737)
- 1.33 MEMORY PHASE MONITORING AND SCHEDULING SYSTEM (17897886)
- 1.34 IDLE MODE TEMPERATURE CONTROL FOR MEMORY SYSTEMS (17900361)
- 1.35 HOST DATA STORAGE SCAN DATA RETENTION RATING (17953182)
- 1.36 FILTERING METRICS ASSOCIATED WITH MEMORY (17823625)
- 1.37 BALANCED CORRECTIVE READ FOR ADDRESSING CELL-TO-CELL INTERFERENCE (18228065)
- 1.38 ACCESS REQUEST REORDERING ACROSS A MULTIPLE-CHANNEL INTERFACE FOR MEMORY-BASED COMMUNICATION QUEUES (17898929)
- 1.39 MEMORY DEVICE OPERATIONS FOR UNALIGNED WRITE OPERATIONS (17822895)
- 1.40 HOST-PREFERRED MEMORY OPERATION (17823314)
- 1.41 MEMORY-SIDE CACHE DIRECTORY-BASED REQUEST QUEUE (17823391)
- 1.42 METHOD OF SUBMITTING WORK TO FABRIC ATTACHED MEMORY (17823462)
- 1.43 CONTROL PARAMETER ADDRESS VIRTUALIZATION (17898803)
- 1.44 ACCESS REQUEST REORDERING FOR MEMORY-BASED COMMUNICATION QUEUES (17899016)
- 1.45 MANAGING DATA COMPACTION FOR ZONES IN MEMORY DEVICES (17899092)
- 1.46 MANAGING COMMAND COMPLETION NOTIFICATION PACING IN A MEMORY SUB-SYSTEM (17900122)
- 1.47 LOGICAL UNIT NUMBER QUEUES AND LOGICAL UNIT NUMBER QUEUE SCHEDULING FOR MEMORY DEVICES (17931934)
- 1.48 MEMORY DEVICES INCLUDING IDLE TIME PREDICTION (17949333)
- 1.49 MANAGING WRITE DISTURB BASED ON IDENTIFICATION OF FREQUENTLY-WRITTEN MEMORY UNITS (18388342)
- 1.50 MECHANISM TO HANDLE BREAKPOINTS IN A MULTI-ELEMENT PROCESSOR (17899710)
- 1.51 QUEUEING ASYNCHRONOUS EVENTS FOR ACCEPTANCE BY THREADS EXECUTING IN A BARREL PROCESSOR (17823468)
- 1.52 Message Queues in Network-Ready Storage Products having Computational Storage Processors (18502713)
- 1.53 CACHING LOOKUP TABLES FOR BLOCK FAMILY ERROR AVOIDANCE (17931937)
- 1.54 AUTO-CALIBRATION OF ERROR DETECTION SIGNALS (17899298)
- 1.55 MEMORY WITH FAIL INDICATORS, INCLUDING MEMORY WITH LED FAIL INDICATORS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS (18223465)
- 1.56 AUTOMATED OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES (17897910)
- 1.57 PARKING THREADS IN BARREL PROCESSOR FOR MANAGING HAZARD CLEARING (17897926)
- 1.58 COMMANDS FOR TESTING ERROR CORRECTION IN A MEMORY DEVICE (17897053)
- 1.59 Read Data Path (17823469)
- 1.60 BLOCK FAILURE PROTECTION FOR ZONE MEMORY SYSTEM (17823365)
- 1.61 PROXIMITY BASED PARITY DATA MANAGEMENT (17897183)
- 1.62 DATA INVERSION AND UNIDIRECTIONAL ERROR DETECTION (17897186)
- 1.63 ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC (17897869)
- 1.64 Read Data Path for a Memory System (17823476)
- 1.65 APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION (17822915)
- 1.66 SECURELY MODIFYING ACCESS TO A DEBUG PORT (17895970)
- 1.67 AUTOMATED GUI-DRIVEN OPROM VALIDATION (18235149)
- 1.68 MULTIMEDIA CARD COMMAND TIMEOUT MEASUREMENT (17894591)
- 1.69 READ CONTROL SIGNAL GENERATION FOR MEMORY (18234636)
- 1.70 MEMORY DEVICES INCLUDING LOGIC NON-VOLATILE MEMORY (17898604)
- 1.71 SYNCHRONIZED REQUEST HANDLING AT A MEMORY DEVICE (17899197)
- 1.72 LOGICAL TO PHYSICAL (L2P) ADDRESS MAPPING WITH FAST L2P TABLE LOAD TIMES (17930117)
- 1.73 SEQUENTIAL GARBAGE COLLECTION (17899137)
- 1.74 MEMORY DEVICE INTERFACE AND METHOD (18215474)
- 1.75 TELEMETRY-CAPABLE MEMORY SUB-SYSTEM (17896883)
- 1.76 VARIABLE EXECUTION TIME ATOMIC OPERATIONS (17899184)
- 1.77 MEMORY SIDE CACHE REQUEST HANDLING (17823323)
- 1.78 RECALL PENDING CACHE LINE EVICTION (17899171)
- 1.79 EVICTING A CACHE LINE WITH PENDING CONTROL REQUEST (17823307)
- 1.80 SILENT CACHE LINE EVICTION (17823408)
- 1.81 PADDING CACHED DATA WITH VALID DATA FOR MEMORY FLUSH COMMANDS (17898779)
- 1.82 PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQUESTS (17897913)
- 1.83 MEASUREMENT COMMAND FOR MEMORY SYSTEMS (18351986)
- 1.84 Asymmetric Read-Write Sequence for Interconnected Dies (17823443)
- 1.85 CONTROLLING AGGREGATION FOR HRAM (18235133)
- 1.86 Erroneous Select Die Access (SDA) Detection (17823432)
- 1.87 Bus Training with Interconnected Dice (17823415)
- 1.88 Bus Training with Interconnected Dice (17823423)
- 1.89 MEMORY DEVICE WITH EMBEDDED DEEP LEARNING ACCELERATOR IN MULTI-CLIENT ENVIRONMENT (17899531)
- 1.90 CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PROCESSOR (17899714)
- 1.91 Multi-Threaded, Self-Scheduling Processor (18386880)
- 1.92 LOOK SELECTION BASED ON RELATIONSHIPS IN A VIRTUAL ENVIRONMENT (18237702)
- 1.93 PREVENTING REPLACEMENT AND CLONE ATTACKS USING A SECURE PROCESSING ENVIRONMENT (17898375)
- 1.94 SECURE BOOT PROCEDURE (18237229)
- 1.95 SECURE BOOT PROCEDURE (18237247)
- 1.96 GENERATING SUGGESTIONS USING EXTENDED REALITY (17823763)
- 1.97 FEATURE INTERACTION USING ATTENTION-BASED FEATURE SELECTION (18237035)
- 1.98 RESOLVING MISPLACED ITEMS IN PHYSICAL RETAIL STORES (17823728)
- 1.99 NAVIGATION PATHS FOR DIRECTING USERS TO LOCATIONS WITHIN A PHYSICAL RETAIL STORE USING EXTENDED REALITY (17823745)
- 1.100 SALE OF VIRTUAL GOODS BASED ON PHYSICAL LOCATION (17899191)
- 1.101 PROCESSING-IN-MEMORY SYSTEM WITH DEEP LEARNING ACCELERATOR FOR ARTIFICIAL INTELLIGENCE (17900018)
- 1.102 OBJECT LOCATION DETERMINATION (17898079)
- 1.103 NAVIGATION PATHS FOR DIRECTING USERS TO FOOD ITEMS BASED ON MEAL PLANS (17823773)
- 1.104 THREE-DIMENSIONAL MODELS OF USERS WEARING CLOTHING ITEMS (17823734)
- 1.105 STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS (17893681)
- 1.106 SEMICONDUCTOR MEMORIES INCLUDING EDGE MATS HAVING FOLDED DIGIT LINES (17893966)
- 1.107 CROSS-TEMPERATURE COMPENSATION IN A MEMORY SUB-SYSTEM (18237816)
- 1.108 CREATING DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY (17895959)
- 1.109 MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY (17899849)
- 1.110 DRIFT COMPENSATION FOR CODEWORDS IN MEMORY (17948423)
- 1.111 GENERATING SEMI-SOFT BIT DATA DURING CORRECTIVE READ OPERATIONS IN MEMORY DEVICES (18198623)
- 1.112 Synchronous Input Buffer Control Using a State Machine (17821740)
- 1.113 Die Disablement (17823458)
- 1.114 DETERMINING READ VOLTAGE OFFSET IN MEMORY DEVICES (17897438)
- 1.115 MANAGING PERFORMANCE AND SERVICE LIFE PREDICTION FOR A MEMORY SUBSYSTEM USING ENVIRONMENTAL FACTORS (17899417)
- 1.116 CONFIGURABLE DATA PROTECTION CIRCUITRY FOR MEMORY DEVICES (17895053)
- 1.117 Word Line Precharging Systems and Methods (17898923)
- 1.118 MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY (17899859)
- 1.119 ROW TRACKING FOR ROW HAMMER MITIGATION (18237786)
- 1.120 Adaptive Memory Registers (17823407)
- 1.121 EFFICIENT PERIODIC BACKEND REFRESH READS FOR REDUCING BIT ERROR RATE IN MEMORY DEVICES (18227139)
- 1.122 Dynamic Address Scramble (17823450)
- 1.123 STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS (17821645)
- 1.124 WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICES (17821646)
- 1.125 WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICES (17893654)
- 1.126 WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICES (17893672)
- 1.127 MEMORY WITH SINGLE TRANSISTOR SUB-WORD LINE DRIVERS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS (17894089)
- 1.128 PARALLEL PIPE LATCH FOR MEMORY ACCESS OPERATIONS (17900075)
- 1.129 SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER EQUIPPED WITH COMPENSATION CIRCUIT (17821775)
- 1.130 MICROELECTRONIC DEVICES INCLUDING CONTROL LOGIC CIRCUITRY OVERLYING MEMORY ARRAYS, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS (17898150)
- 1.131 STREAMING MODE FOR ACCESSING MEMORY CELLS IN A MEMORY DEVICE (17898346)
- 1.132 DRIFT CORRECTION IN SLC AND MLC MEMORY DEVICES (17898392)
- 1.133 MEMORY DEVICES WITH A LOWER EFFECTIVE PROGRAM VERIFY LEVEL (18234429)
- 1.134 DRIFT COMPENSATION FOR CODEWORDS IN MEMORY (17948520)
- 1.135 DRIFT COMPENSATION FOR CODEWORDS IN MEMORY (17948582)
- 1.136 FORWARD LOOKING ALGORITHM FOR VERTICAL INTEGRATED CROSS-POINT ARRAY MEMORY (17897021)
- 1.137 CASCODED SENSE AMPLIFIERS FOR SELF-SELECTING MEMORY (17896963)
- 1.138 TRIGGERING OF STRONGER WRITE PULSES IN A MEMORY DEVICE BASED ON PRIOR READ OPERATIONS (17895988)
- 1.139 Memory Circuitry And Method Used In Forming Memory Circuitry (17896775)
- 1.140 Memory Circuitry And Method Used In Forming Memory Circuitry (17897460)
- 1.141 SELF-SUPPORTING SGD STADIUM (17898827)
- 1.142 Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17971443)
- 1.143 MEMORY ARRAY STRUCTURES AND METHODS OF THEIR FABRICATION (18234046)
- 1.144 MICROELECTRONIC DEVICES WITH MIRRORED BLOCKS OF MULTI-SET STAIRCASED STADIUMS, AND RELATED SYSTEMS AND METHODS (18364397)
- 1.145 STAIRCASE FORMATION IN A MEMORY ARRAY (17822712)
- 1.146 PADDING IN FLASH MEMORY BLOCKS (17897184)
- 1.147 DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY (18237815)
- 1.148 PARTIAL BLOCK READ VOLTAGE OFFSET (17823191)
- 1.149 APPARATUS AND METHODS FOR PROGRAMMING DATA STATES OF MEMORY CELLS (17894248)
- 1.150 TWO-PASS CORRECTIVE PROGRAMMING FOR MEMORY CELLS THAT STORE MULTIPLE BITS AND POWER LOSS MANAGEMENT FOR TWO-PASS CORRECTIVE PROGRAMMING (17899409)
- 1.151 DRIFT COMPENSATION FOR CODEWORDS IN MEMORY (17948556)
- 1.152 ERASE SUSPEND WITH CONFIGURABLE FORWARD PROGRESS (17893755)
- 1.153 NAND DETECT EMPTY PAGE SCAN (17898043)
- 1.154 ERASE PULSE LOOP DEPENDENT ADJUSTMENT OF SELECT GATE ERASE BIAS VOLTAGE (18235183)
- 1.155 DISCHARGE CIRCUITS (17897448)
- 1.156 CODING TO DECREASE ERROR RATE DISCREPANCY BETWEEN PAGES (17894398)
- 1.157 SUSPENDING MEMORY ERASE OPERATIONS TO PERFORM HIGHER PRIORITY MEMORY COMMANDS (17931935)
- 1.158 MEMORY DEVICE PRODUCING METADATA CHARACTERIZING APPLIED READ VOLTAGE LEVEL WITH RESPECT TO VOLTAGE DISTRIBUTIONS (18228291)
- 1.159 READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS (17895886)
- 1.160 MANAGING DEFECTIVE BLOCKS DURING MULTI-PLANE PROGRAMMING OPERATIONS IN MEMORY DEVICES (17897441)
- 1.161 CORRECTIVE PROGRAM VERIFY OPERATION WITH IMPROVED READ WINDOW BUDGET RETENTION (18233420)
- 1.162 MEMORY DEVICES WITH PROGRAM VERIFY LEVELS BASED ON COMPENSATION VALUES (18239193)
- 1.163 INTEGRATED FLAG BYTE READ DURING FAILED BYTE COUNT READ COMPENSATION IN A MEMORY DEVICE (18237309)
- 1.164 BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTION DECODER THROUGHPUT SPECIFICATIONS (18231514)
- 1.165 APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION (17822909)
- 1.166 APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION (17822912)
- 1.167 ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES (17894528)
- 1.168 BLOCK FAMILY ERROR AVOIDANCE BIN SCANS AFTER MEMORY DEVICE POWER-ON (17898725)
- 1.169 MEMORY WITH PARALLEL MAIN AND TEST INTERFACES (17821676)
- 1.170 MEMORY DEVICE WITH REDUNDANCY FOR PAGE-BASED REPAIR (17823740)
- 1.171 SYSTEMS AND METHODS FOR TESTING REDUNDANT FUSE LATCHES IN A MEMORY DEVICE (17822032)
- 1.172 CONDUCTIVE NODE INDUCTION APPARATUS (17895966)
- 1.173 STAIRCASE FORMATION IN A MEMORY ARRAY (17896919)
- 1.174 STRESS MITIGATION FOR THREE-DIMENSIONAL METAL CONTACTS (18234111)
- 1.175 SEMICONDUCTOR DEVICE CIRCUITRY FORMED THROUGH VOLUMETRIC EXPANSION (18237174)
- 1.176 HEAT SPREADER APPARATUS WITH MAGNETIC ATTACHMENTS ON PRINTED WIRING BOARD ASSEMBLIES, RELATED METHODS AND ELECTRONIC SYSTEMS (17821871)
- 1.177 SPLIT VIA STRUCTURE FOR SEMICONDUCTOR DEVICE PACKAGING (17894102)
- 1.178 PACKAGE SUBSTRATE FOR A SEMICONDUCTOR DEVICE (17897155)
- 1.179 SEMICONDUCTOR PACKAGING WITH REDUCED STANDOFF HEIGHT (17894063)
- 1.180 MULTI-CHIP PACKAGE WITH ENHANCED CONDUCTIVE LAYER ADHESION (17823349)
- 1.181 SEMICONDUCTOR DEVICE ASSEMBLIES HAVING FACE-TO-FACE SUBASSEMBLIES, AND METHODS FOR MAKING THE SAME (17899577)
- 1.182 FOLDED STAIRCASE VIA ROUTING FOR MEMORY (17893718)
- 1.183 METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS (17898107)
- 1.184 SEMICONDUCTOR DEVICE ASSEMBLIES WITH COPLANAR INTERCONNECT STRUCTURES, AND METHODS FOR MAKING THE SAME (17899586)
- 1.185 MICROELECTRONIC DEVICES INCLUDING STADIUM STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS (17822421)
- 1.186 METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS (17823472)
- 1.187 METHODS OF FORMING MICROELECTRONIC DEVICES INCLUDING STAIR STEP STRUCTURES (18504901)
- 1.188 Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17900064)
- 1.189 Memory Circuitry And Method Used In Forming Memory Circuitry (17944343)
- 1.190 SEMICONDUCTOR DEVICE ASSEMBLY SUBSTRATES WITH TUNNELED INTERCONNECTS, AND METHODS FOR MAKING THE SAME (17893968)
- 1.191 MEMORY ARRAY STRUCTURES AND METHODS OF THEIR FABRICATION (17961025)
- 1.192 SEMICONDUCTOR DEVICE INTERCONNECTS FORMED THROUGH VOLUMETRIC EXPANSION (18199741)
- 1.193 SEMICONDUCTOR DIE STACKS AND ASSOCIATED SYSTEMS AND METHODS (18220734)
- 1.194 SEMICONDUCTOR DEVICE WITH VOLUMETRICALLY-EXPANDED SIDE-CONNECTED INTERCONNECTS (18237225)
- 1.195 SEMICONDUCTOR CONDUCTIVE PILLAR DEVICE AND METHOD (17823162)
- 1.196 SOLDER BASED HYBRID BONDING FOR FINE PITCH AND THIN BLT INTERCONNECTION (18502389)
- 1.197 SUBSTRATES WITH SPACERS, INCLUDING SUBSTRATES WITH SOLDER RESIST SPACERS, AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS (17899522)
- 1.198 SEMICONDUCTOR DEVICE WITH A POLYMER LAYER (17899574)
- 1.199 DIE EDGE FILLET AND 3D-PRINTED CNT AS BENDING STRESS BUFFER (17823189)
- 1.200 SEMICONDUCTOR DEVICE ASSEMBLIES WITH BALANCED WIRES, AND ASSOCIATED METHODS (17898368)
- 1.201 WIRE BONDING DIRECTLY ON EXPOSED CONDUCTIVE VIAS AND INTERCONNECTS AND RELATED SYSTEMS AND METHODS (17899550)
- 1.202 PIEZOELECTRIC MATERIALS FOR ON-DIE THERMAL ENHANCEMENT OF HYBRID BONDING AND ASSOCIATED SYSTEMS AND METHODS (17898330)
- 1.203 EMBEDDED NANOPARTICLES FOR ON-DIE THERMAL ENHANCEMENT OF HYBRID BONDING AND ASSOCIATED SYSTEMS AND METHODS (17898356)
- 1.204 SEMICONDUCTOR DEVICE CIRCUITRY FORMED FROM REMOTE RESERVOIRS (18237202)
- 1.205 EXTENDED BOND PAD FOR SEMICONDUCTOR DEVICE ASSEMBLIES (17896030)
- 1.206 SEMICONDUCTOR DEVICES, ASSEMBLIES, AND ASSOCIATED METHODS (17893941)
- 1.207 SEMICONDUCTOR DEVICE WITH CIRCUIT COMPONENTS FORMED THROUGH INTER-DIE CONNECTIONS (18237259)
- 1.208 STACKED CAPACITORS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS (17899592)
- 1.209 MODULAR SYSTEMS IN PACKAGES, AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS (17897156)
- 1.210 APPARATUS INCLUDING ADJUSTED WELLS AND METHODS OF MANUFACTURING THE SAME (17898184)
- 1.211 CONTACT ARRANGEMENTS FOR TRANSISTORS (18234129)
- 1.212 TRANSISTORS WITH MITIGATED FREE BODY EFFECT (18237206)
- 1.213 SYSTEMS AND TECHNIQUES FOR TIMING MISMATCH REDUCTION (17895826)
- 1.214 CLOUD STORAGE WITH ENHANCED DATA PRIVACY (17898382)
- 1.215 SECURELY SHARING DATA AND ACCESS PERMISSIONS IN A CLOUD ENVIRONMENT (17899177)
- 1.216 GENERATING A SHARED SECRET FOR AN ELECTRONIC SYSTEM (18221790)
- 1.217 GROUP DIGITAL CERTIFICATES FOR DEVICE ONBOARDING (17895975)
- 1.218 SEMICONDUCTOR PACKAGING WITH REDUCED STANDOFF HEIGHT (17894070)
- 1.219 SUBSTRATES WITH CONTINUOUS SLOT VIAS (17899477)
- 1.220 INTEGRATED BRACKET FOR ENHANCED HEAT DISSIPATION (18239427)
- 1.221 COMPACT MICROELECTRONIC 6T SRAM MEMORY DEVICES, AND RELATED SYSTEMS AND METHODS (17898060)
- 1.222 MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE DATA LINES (18238269)
- 1.223 FABRICATION METHOD OF A LATERAL 3D MEMORY DEVICE (17895017)
- 1.224 MICROELECTRONIC DEVICES, RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS (17898233)
- 1.225 BOTTOM ELECTRODE CONTACT FOR A VERTICAL THREE-DIMENSIONAL MEMORY (18387641)
- 1.226 CONDUCTIVE STRUCTURES (17896039)
- 1.227 SHALLOW TRENCH ISOLATION RECESS CONTROL (18234145)
- 1.228 SACRIFICIAL POLYSILICON IN INTEGRATION OF MEMORY ARRAY WITH PERIPHERY (18236544)
- 1.229 INTEGRATION OF MEMORY ARRAY WITH PERIPHERY (18236566)
- 1.230 MEMORY ARRAY - PERIPHERY INTEGRATION WITH SPLIT BARRIER METAL STACK (18236579)
- 1.231 METAL SILICIDE IN INTEGRATION OF MEMORY ARRAY WITH PERIPHERY (18236556)
- 1.232 MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES FORMED FROM THIN-FILM TRANSISTORS (17898232)
- 1.233 MICROELECTRONIC DEVICES WITH A TIERED STACK OF CONDUCTIVE, INSULATIVE, AND PARTIALLY-SACRIFICIAL STRUCTURES, AND RELATED SYSTEMS AND METHODS (17822101)
- 1.234 ELECTRONIC DEVICES COMPRISING BLOCKING REGIONS, AND RELATED ELECTRONIC SYSTEMS AND METHODS (17823276)
- 1.235 Memory Circuitry And Method Used In Forming Memory Circuitry (17897399)
- 1.236 Memory Circuitry And Method Used In Forming Memory Circuitry (17897516)
- 1.237 ELECTRONIC DEVICES COMPRISING A STEPPED PILLAR REGION, AND RELATED METHODS (17897976)
- 1.238 MEMORY DEVICE INCLUDING STAIRCASE STRUCTURES AND ADJACENT TRENCH STRUCTURES (18237661)
- 1.239 Memory Circuitry And Method Used In Forming Memory Circuitry (17893436)
- 1.240 Memory Circuitry And Method Used In Forming Memory Circuitry (17897350)
- 1.241 MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND MEMORY ELEMENT BETWEEN CHANNEL REGION AND CONDUCTIVE PLATE (18238291)
- 1.242 Integrated Assemblies Comprising Hydrogen Diffused Within Two or More Different Semiconductor Materials, and Methods of Forming Integrated Assemblies (18387921)
Patent applications for Micron Technology, Inc. on February 29th, 2024
MULTI-SENSOR TEST DEVICE FOR QUALITY CONTROL SCANNING (17823806)
Main Inventor
Theodore G. DOROS
THERMAL IMPROVEMENTS FOR MEMORY SUB-SYSTEMS (18235169)
Main Inventor
Suresh Reddy Yarragunta
MEMORY DEVICE CLOCK MAPPING (17897957)
Main Inventor
Kallol Mazumder
MEMORY WITH SWITCHABLE CHANNELS (17823909)
Main Inventor
Sundararajan Sankaranarayanan
MEMORY DEVICE LOG DATA STORAGE (17822250)
Main Inventor
Scheheresade VIRANI
ADDRESS TRANSLATION METADATA COMPRESSION IN MEMORY DEVICES (17895696)
Main Inventor
Brian Toronyi
VARYING MEMORY ERASE DEPTH ACCORDING TO BLOCK CHARACTERISTICS (18223933)
Main Inventor
Sriteja Yamparala
BALANCING PERFORMANCE BETWEEN INTERFACE PORTS IN A MEMORY SUB-SYSTEM (17900120)
Main Inventor
Raja V.S. Halaharivi
MULTIPLE MEMORY BLOCK ERASE OPERATION (18233433)
Main Inventor
Deping He
UTILIZING LAST SUCCESSFUL READ VOLTAGE LEVEL IN MEMORY ACCESS OPERATIONS (17894540)
Main Inventor
Kyungjin Kim
MEMORY BLOCK ERASE PROTOCOL (17898333)
Main Inventor
Chun Sum Yeung
ACCESSING MEMORY DEVICES VIA SWITCHABLE CHANNELS (17898160)
Main Inventor
Chulbum Kim
EFFECTIVE STORAGE ALLOCATION FOR SEQUENTIALLY-WRITTEN MEMORY DEVICES (18502764)
Main Inventor
Luca Bert
DYNAMIC WEAR LEVELING TECHNIQUES (17899341)
Main Inventor
Luigi Esposito
APPARATUS WITH SIGNAL QUALITY FEEDBACK (17897153)
Main Inventor
Jackson Callaghan
CROSS-TEMPERATURE COMPENSATION BASED ON MEDIA ENDURANCE IN MEMORY DEVICES (17897784)
Main Inventor
Hyungseok Kim
REDUCING BIT ERROR RATE IN MEMORY DEVICES (18219023)
Main Inventor
Tingjun Xie
ASYMMETRIC PASS THROUGH VOLTAGE FOR REDUCTION OF CELL-TO-CELL INTERFERENCE (18236087)
Main Inventor
Augusto Benvenuti
MEMORY CHIP TEST PAD ACCESS MANAGEMENT TO FACILITATE DATA SECURITY (17946738)
Main Inventor
Qi Dong
PARTITIONING SYSTEM DATA FROM USER DATA IN MEMORY (17894343)
Main Inventor
Michael Burk
SHARED MEMORY SNAPSHOTS (17895918)
Main Inventor
John Groves
TRIPLE ACTIVATE COMMAND ROW ADDRESS LATCHING (17899222)
Main Inventor
Kwang-Ho Cho
ROW ADDRESS LATCHING FOR MULTIPLE ACTIVATE COMMAND PROTOCOL (17899305)
Main Inventor
Kwang-Ho Cho
COMBINED MEMORY MODULE LOGIC DEVICES FOR REDUCED COST AND IMPROVED FUNCTIONALITY (18223249)
Main Inventor
Matthew A. Prather
SINGLE-BIT ERROR INDICATION FOR A MEMORY BUILT-IN SELF-TEST (17821924)
Main Inventor
Scott E. SCHAEFER
TWO-TIER DEFECT SCAN MANAGEMENT (17894794)
Main Inventor
Kishore Kumar Muchherla
SELECTIVE DATA MAP UNIT ACCESS (17822606)
Main Inventor
Marco REDAELLI
HOST-INITIATED AND AUTO-INITIATED NON-VOLATILE MEMORY REFRESH (17897940)
Main Inventor
Marco Redaelli
METHOD OF EFFICIENTLY IDENTIFYING ROLLBACK REQUESTS (17823470)
Main Inventor
Tony M. Brewer
READ OPERATIONS FOR MIXED DATA (17822893)
Main Inventor
Scheheresade VIRANI
DEFERRED ZONE ADJUSTMENT IN ZONE MEMORY SYSTEM (17899801)
Main Inventor
Oyvind Haehre
SUPER BLOCK MANAGEMENT FOR EFFICIENT UTILIZATION (18237737)
Main Inventor
Xiangang Luo
MEMORY PHASE MONITORING AND SCHEDULING SYSTEM (17897886)
Main Inventor
David Andrew Roberts
IDLE MODE TEMPERATURE CONTROL FOR MEMORY SYSTEMS (17900361)
Main Inventor
Francesco Basso
HOST DATA STORAGE SCAN DATA RETENTION RATING (17953182)
Main Inventor
Vamsi Pavan Rayaprolu
FILTERING METRICS ASSOCIATED WITH MEMORY (17823625)
Main Inventor
Dung Viet NGUYEN
BALANCED CORRECTIVE READ FOR ADDRESSING CELL-TO-CELL INTERFERENCE (18228065)
Main Inventor
Giovanni Maria Paolucci
ACCESS REQUEST REORDERING ACROSS A MULTIPLE-CHANNEL INTERFACE FOR MEMORY-BASED COMMUNICATION QUEUES (17898929)
Main Inventor
Michael Keith Dugan
MEMORY DEVICE OPERATIONS FOR UNALIGNED WRITE OPERATIONS (17822895)
Main Inventor
Scheheresade VIRANI
HOST-PREFERRED MEMORY OPERATION (17823314)
Main Inventor
Tony M. Brewer
MEMORY-SIDE CACHE DIRECTORY-BASED REQUEST QUEUE (17823391)
Main Inventor
Tony M. Brewer
METHOD OF SUBMITTING WORK TO FABRIC ATTACHED MEMORY (17823462)
Main Inventor
Tony M. Brewer
CONTROL PARAMETER ADDRESS VIRTUALIZATION (17898803)
Main Inventor
Tony M. Brewer
ACCESS REQUEST REORDERING FOR MEMORY-BASED COMMUNICATION QUEUES (17899016)
Main Inventor
Michael Keith Dugan
MANAGING DATA COMPACTION FOR ZONES IN MEMORY DEVICES (17899092)
Main Inventor
Naveen Bolisetty
MANAGING COMMAND COMPLETION NOTIFICATION PACING IN A MEMORY SUB-SYSTEM (17900122)
Main Inventor
Raja V.S. Halaharivi
LOGICAL UNIT NUMBER QUEUES AND LOGICAL UNIT NUMBER QUEUE SCHEDULING FOR MEMORY DEVICES (17931934)
Main Inventor
Shakeel Isamohiuddin BUKHARI
MEMORY DEVICES INCLUDING IDLE TIME PREDICTION (17949333)
Main Inventor
Tyler L. Betz
MANAGING WRITE DISTURB BASED ON IDENTIFICATION OF FREQUENTLY-WRITTEN MEMORY UNITS (18388342)
Main Inventor
Tingjun Xie
MECHANISM TO HANDLE BREAKPOINTS IN A MULTI-ELEMENT PROCESSOR (17899710)
Main Inventor
Bryan Hornung
QUEUEING ASYNCHRONOUS EVENTS FOR ACCEPTANCE BY THREADS EXECUTING IN A BARREL PROCESSOR (17823468)
Main Inventor
Christopher Baronne
Message Queues in Network-Ready Storage Products having Computational Storage Processors (18502713)
Main Inventor
Luca Bert
CACHING LOOKUP TABLES FOR BLOCK FAMILY ERROR AVOIDANCE (17931937)
Main Inventor
Shakeel Isamohiuddin BUKHARI
AUTO-CALIBRATION OF ERROR DETECTION SIGNALS (17899298)
Main Inventor
Hao Ge
MEMORY WITH FAIL INDICATORS, INCLUDING MEMORY WITH LED FAIL INDICATORS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS (18223465)
Main Inventor
Aaron Jannusch
AUTOMATED OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES (17897910)
Main Inventor
Jay Sarkar
PARKING THREADS IN BARREL PROCESSOR FOR MANAGING HAZARD CLEARING (17897926)
Main Inventor
Christopher Baronne
COMMANDS FOR TESTING ERROR CORRECTION IN A MEMORY DEVICE (17897053)
Main Inventor
Francesco Lupo
Read Data Path (17823469)
Main Inventor
Nicola Del Gatto
BLOCK FAILURE PROTECTION FOR ZONE MEMORY SYSTEM (17823365)
Main Inventor
Sanjay Subbarao
PROXIMITY BASED PARITY DATA MANAGEMENT (17897183)
Main Inventor
Yu-Chung Lien
DATA INVERSION AND UNIDIRECTIONAL ERROR DETECTION (17897186)
Main Inventor
Steffen Buch
ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC (17897869)
Main Inventor
Kishore Kumar Muchherla
Read Data Path for a Memory System (17823476)
Main Inventor
Nicola Del Gatto
APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION (17822915)
Main Inventor
Sujeet Ayyapureddi
SECURELY MODIFYING ACCESS TO A DEBUG PORT (17895970)
Main Inventor
Zhan Liu
AUTOMATED GUI-DRIVEN OPROM VALIDATION (18235149)
Main Inventor
Shiva Pahwa
MULTIMEDIA CARD COMMAND TIMEOUT MEASUREMENT (17894591)
Main Inventor
Domenico Punzo
READ CONTROL SIGNAL GENERATION FOR MEMORY (18234636)
Main Inventor
Jaeil Kim
MEMORY DEVICES INCLUDING LOGIC NON-VOLATILE MEMORY (17898604)
Main Inventor
Vikas Rana
SYNCHRONIZED REQUEST HANDLING AT A MEMORY DEVICE (17899197)
Main Inventor
Tony M. Brewer
LOGICAL TO PHYSICAL (L2P) ADDRESS MAPPING WITH FAST L2P TABLE LOAD TIMES (17930117)
Main Inventor
Steven R. NARUM
SEQUENTIAL GARBAGE COLLECTION (17899137)
Main Inventor
David A. Palmer
MEMORY DEVICE INTERFACE AND METHOD (18215474)
Main Inventor
Brent Keeth
TELEMETRY-CAPABLE MEMORY SUB-SYSTEM (17896883)
Main Inventor
David Andrew Roberts
VARIABLE EXECUTION TIME ATOMIC OPERATIONS (17899184)
Main Inventor
Dean E. Walker
MEMORY SIDE CACHE REQUEST HANDLING (17823323)
Main Inventor
Dean E. Walker
RECALL PENDING CACHE LINE EVICTION (17899171)
Main Inventor
Dean E. Walker
EVICTING A CACHE LINE WITH PENDING CONTROL REQUEST (17823307)
Main Inventor
Tony M. Brewer
SILENT CACHE LINE EVICTION (17823408)
Main Inventor
Tony M. Brewer
PADDING CACHED DATA WITH VALID DATA FOR MEMORY FLUSH COMMANDS (17898779)
Main Inventor
Kishore Kumar Muchherla
PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQUESTS (17897913)
Main Inventor
Christopher Baronne
MEASUREMENT COMMAND FOR MEMORY SYSTEMS (18351986)
Main Inventor
Lance W. Dover
Asymmetric Read-Write Sequence for Interconnected Dies (17823443)
Main Inventor
Hyun Yoo Lee
CONTROLLING AGGREGATION FOR HRAM (18235133)
Main Inventor
John Maroney
Erroneous Select Die Access (SDA) Detection (17823432)
Main Inventor
Yang Lu
Bus Training with Interconnected Dice (17823415)
Main Inventor
Francesco Douglas Verna-Ketel
Bus Training with Interconnected Dice (17823423)
Main Inventor
Yang Lu
MEMORY DEVICE WITH EMBEDDED DEEP LEARNING ACCELERATOR IN MULTI-CLIENT ENVIRONMENT (17899531)
Main Inventor
Dmitri Yudanov
CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PROCESSOR (17899714)
Main Inventor
Bryan Hornung
Multi-Threaded, Self-Scheduling Processor (18386880)
Main Inventor
Tony M. Brewer
LOOK SELECTION BASED ON RELATIONSHIPS IN A VIRTUAL ENVIRONMENT (18237702)
Main Inventor
Carla L. Christensen
PREVENTING REPLACEMENT AND CLONE ATTACKS USING A SECURE PROCESSING ENVIRONMENT (17898375)
Main Inventor
Zhan Liu
SECURE BOOT PROCEDURE (18237229)
Main Inventor
Alessandro Orlando
SECURE BOOT PROCEDURE (18237247)
Main Inventor
Alessandro Orlando
GENERATING SUGGESTIONS USING EXTENDED REALITY (17823763)
Main Inventor
Saideep TIKU
FEATURE INTERACTION USING ATTENTION-BASED FEATURE SELECTION (18237035)
Main Inventor
Mritunjay Kumar
RESOLVING MISPLACED ITEMS IN PHYSICAL RETAIL STORES (17823728)
Main Inventor
Saideep TIKU
NAVIGATION PATHS FOR DIRECTING USERS TO LOCATIONS WITHIN A PHYSICAL RETAIL STORE USING EXTENDED REALITY (17823745)
Main Inventor
Saideep TIKU
SALE OF VIRTUAL GOODS BASED ON PHYSICAL LOCATION (17899191)
Main Inventor
John D. Hopkins
PROCESSING-IN-MEMORY SYSTEM WITH DEEP LEARNING ACCELERATOR FOR ARTIFICIAL INTELLIGENCE (17900018)
Main Inventor
Xinyu Wu
OBJECT LOCATION DETERMINATION (17898079)
Main Inventor
Maithilee Motlag
NAVIGATION PATHS FOR DIRECTING USERS TO FOOD ITEMS BASED ON MEAL PLANS (17823773)
Main Inventor
Saideep TIKU
THREE-DIMENSIONAL MODELS OF USERS WEARING CLOTHING ITEMS (17823734)
Main Inventor
Saideep TIKU
STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS (17893681)
Main Inventor
Fatma Arzum Simsek-Ege
SEMICONDUCTOR MEMORIES INCLUDING EDGE MATS HAVING FOLDED DIGIT LINES (17893966)
Main Inventor
Hirokazu Ato
CROSS-TEMPERATURE COMPENSATION IN A MEMORY SUB-SYSTEM (18237816)
Main Inventor
Andrea Giovanni Xotta
CREATING DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY (17895959)
Main Inventor
Jiewei Chen
MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY (17899849)
Main Inventor
Si Hong Kim
DRIFT COMPENSATION FOR CODEWORDS IN MEMORY (17948423)
Main Inventor
Marco Sforzin
GENERATING SEMI-SOFT BIT DATA DURING CORRECTIVE READ OPERATIONS IN MEMORY DEVICES (18198623)
Main Inventor
Phong Sy Nguyen
Synchronous Input Buffer Control Using a State Machine (17821740)
Main Inventor
Kallol Mazumder
Die Disablement (17823458)
Main Inventor
Yang Lu
DETERMINING READ VOLTAGE OFFSET IN MEMORY DEVICES (17897438)
Main Inventor
Robert W. Mason
MANAGING PERFORMANCE AND SERVICE LIFE PREDICTION FOR A MEMORY SUBSYSTEM USING ENVIRONMENTAL FACTORS (17899417)
Main Inventor
Abhilash Ramamurthy Nag
CONFIGURABLE DATA PROTECTION CIRCUITRY FOR MEMORY DEVICES (17895053)
Main Inventor
Marco Sforzin
Word Line Precharging Systems and Methods (17898923)
Main Inventor
Angelo Visconti
MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY (17899859)
Main Inventor
Si Hong Kim
ROW TRACKING FOR ROW HAMMER MITIGATION (18237786)
Main Inventor
Emanuele Confalonieri
Adaptive Memory Registers (17823407)
Main Inventor
John Christopher Sancon
EFFICIENT PERIODIC BACKEND REFRESH READS FOR REDUCING BIT ERROR RATE IN MEMORY DEVICES (18227139)
Main Inventor
Tingjun Xie
Dynamic Address Scramble (17823450)
Main Inventor
Erik T. Barmon
STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS (17821645)
Main Inventor
Fatma Arzum Simsek-Ege
WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICES (17821646)
Main Inventor
Fatma Arzum Simsek-Ege
WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICES (17893654)
Main Inventor
Fatma Arzum Simsek-Ege
WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICES (17893672)
Main Inventor
Fatma Arzum SIMSEK-EGE
MEMORY WITH SINGLE TRANSISTOR SUB-WORD LINE DRIVERS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS (17894089)
Main Inventor
Tae H. Kim
PARALLEL PIPE LATCH FOR MEMORY ACCESS OPERATIONS (17900075)
Main Inventor
Jaeil Kim
SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER EQUIPPED WITH COMPENSATION CIRCUIT (17821775)
Main Inventor
KYOICHI NAGATA
MICROELECTRONIC DEVICES INCLUDING CONTROL LOGIC CIRCUITRY OVERLYING MEMORY ARRAYS, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS (17898150)
Main Inventor
Yuan He
STREAMING MODE FOR ACCESSING MEMORY CELLS IN A MEMORY DEVICE (17898346)
Main Inventor
Andrea Martinelli
DRIFT CORRECTION IN SLC AND MLC MEMORY DEVICES (17898392)
Main Inventor
Christophe Vincent Antoine Laurent
MEMORY DEVICES WITH A LOWER EFFECTIVE PROGRAM VERIFY LEVEL (18234429)
Main Inventor
Massimo Ernesto Bertuccio
DRIFT COMPENSATION FOR CODEWORDS IN MEMORY (17948520)
Main Inventor
Marco Sforzin
DRIFT COMPENSATION FOR CODEWORDS IN MEMORY (17948582)
Main Inventor
Marco Sforzin
FORWARD LOOKING ALGORITHM FOR VERTICAL INTEGRATED CROSS-POINT ARRAY MEMORY (17897021)
Main Inventor
Ferdinando Bedeschi
CASCODED SENSE AMPLIFIERS FOR SELF-SELECTING MEMORY (17896963)
Main Inventor
Umberto di Vincenzo
TRIGGERING OF STRONGER WRITE PULSES IN A MEMORY DEVICE BASED ON PRIOR READ OPERATIONS (17895988)
Main Inventor
Zhongyuan Lu
Memory Circuitry And Method Used In Forming Memory Circuitry (17896775)
Main Inventor
Jiewei Chen
Memory Circuitry And Method Used In Forming Memory Circuitry (17897460)
Main Inventor
John D. Hopkins
SELF-SUPPORTING SGD STADIUM (17898827)
Main Inventor
Anna Maria Conti
Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17971443)
Main Inventor
Yongjun Jeff Hu
MEMORY ARRAY STRUCTURES AND METHODS OF THEIR FABRICATION (18234046)
Main Inventor
Jae Kyu Choi
MICROELECTRONIC DEVICES WITH MIRRORED BLOCKS OF MULTI-SET STAIRCASED STADIUMS, AND RELATED SYSTEMS AND METHODS (18364397)
Main Inventor
Lifang Xu
STAIRCASE FORMATION IN A MEMORY ARRAY (17822712)
Main Inventor
Alyssa N. Scarbrough
PADDING IN FLASH MEMORY BLOCKS (17897184)
Main Inventor
Yu-Chung Lien
DYNAMIC LATCHES ABOVE A THREE-DIMENSIONAL NON-VOLATILE MEMORY ARRAY (18237815)
Main Inventor
Jiewei Chen
PARTIAL BLOCK READ VOLTAGE OFFSET (17823191)
Main Inventor
Zhongguang XU
APPARATUS AND METHODS FOR PROGRAMMING DATA STATES OF MEMORY CELLS (17894248)
Main Inventor
Koichi Kawai
TWO-PASS CORRECTIVE PROGRAMMING FOR MEMORY CELLS THAT STORE MULTIPLE BITS AND POWER LOSS MANAGEMENT FOR TWO-PASS CORRECTIVE PROGRAMMING (17899409)
Main Inventor
Kishore Kumar Muchherla
DRIFT COMPENSATION FOR CODEWORDS IN MEMORY (17948556)
Main Inventor
Marco Sforzin
ERASE SUSPEND WITH CONFIGURABLE FORWARD PROGRESS (17893755)
Main Inventor
Phil REUSSWIG
NAND DETECT EMPTY PAGE SCAN (17898043)
Main Inventor
Christina PAPAGIANNI
ERASE PULSE LOOP DEPENDENT ADJUSTMENT OF SELECT GATE ERASE BIAS VOLTAGE (18235183)
Main Inventor
Ching-Huang Lu
DISCHARGE CIRCUITS (17897448)
Main Inventor
Kenneth W. Marr
CODING TO DECREASE ERROR RATE DISCREPANCY BETWEEN PAGES (17894398)
Main Inventor
Curtis Egan
SUSPENDING MEMORY ERASE OPERATIONS TO PERFORM HIGHER PRIORITY MEMORY COMMANDS (17931935)
Main Inventor
Shakeel Isamohiuddin BUKHARI
MEMORY DEVICE PRODUCING METADATA CHARACTERIZING APPLIED READ VOLTAGE LEVEL WITH RESPECT TO VOLTAGE DISTRIBUTIONS (18228291)
Main Inventor
Dung Viet Nguyen
READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS (17895886)
Main Inventor
Nicola Ciocchini
MANAGING DEFECTIVE BLOCKS DURING MULTI-PLANE PROGRAMMING OPERATIONS IN MEMORY DEVICES (17897441)
Main Inventor
Robert W. Mason
CORRECTIVE PROGRAM VERIFY OPERATION WITH IMPROVED READ WINDOW BUDGET RETENTION (18233420)
Main Inventor
Ching-Huang Lu
MEMORY DEVICES WITH PROGRAM VERIFY LEVELS BASED ON COMPENSATION VALUES (18239193)
Main Inventor
Tomoko Ogura Iwasaki
INTEGRATED FLAG BYTE READ DURING FAILED BYTE COUNT READ COMPENSATION IN A MEMORY DEVICE (18237309)
Main Inventor
Nagendra Prasad Ganesh Rao
BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTION DECODER THROUGHPUT SPECIFICATIONS (18231514)
Main Inventor
Guang Hu
APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION (17822909)
Main Inventor
Sujeet Ayyapureddi
APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION (17822912)
Main Inventor
Sujeet Ayyapureddi
ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES (17894528)
Main Inventor
Li-Te Chang
BLOCK FAMILY ERROR AVOIDANCE BIN SCANS AFTER MEMORY DEVICE POWER-ON (17898725)
Main Inventor
Guang Hu
MEMORY WITH PARALLEL MAIN AND TEST INTERFACES (17821676)
Main Inventor
James Brian Johnson
MEMORY DEVICE WITH REDUNDANCY FOR PAGE-BASED REPAIR (17823740)
Main Inventor
Alan John Wilson
SYSTEMS AND METHODS FOR TESTING REDUNDANT FUSE LATCHES IN A MEMORY DEVICE (17822032)
Main Inventor
Yoshinori Fujiwara
CONDUCTIVE NODE INDUCTION APPARATUS (17895966)
Main Inventor
Carlos Franco
STAIRCASE FORMATION IN A MEMORY ARRAY (17896919)
Main Inventor
Alyssa N. Scarbrough
STRESS MITIGATION FOR THREE-DIMENSIONAL METAL CONTACTS (18234111)
Main Inventor
Chandra S. Tiwari
SEMICONDUCTOR DEVICE CIRCUITRY FORMED THROUGH VOLUMETRIC EXPANSION (18237174)
Main Inventor
Kyle K. Kirby
HEAT SPREADER APPARATUS WITH MAGNETIC ATTACHMENTS ON PRINTED WIRING BOARD ASSEMBLIES, RELATED METHODS AND ELECTRONIC SYSTEMS (17821871)
Main Inventor
Charles E. Siko
SPLIT VIA STRUCTURE FOR SEMICONDUCTOR DEVICE PACKAGING (17894102)
Main Inventor
Hong Wan Ng
PACKAGE SUBSTRATE FOR A SEMICONDUCTOR DEVICE (17897155)
Main Inventor
Seng Kim Ye
SEMICONDUCTOR PACKAGING WITH REDUCED STANDOFF HEIGHT (17894063)
Main Inventor
Ling Pan
MULTI-CHIP PACKAGE WITH ENHANCED CONDUCTIVE LAYER ADHESION (17823349)
Main Inventor
Hong Wan Ng
SEMICONDUCTOR DEVICE ASSEMBLIES HAVING FACE-TO-FACE SUBASSEMBLIES, AND METHODS FOR MAKING THE SAME (17899577)
Main Inventor
Thiagarajan Raman
FOLDED STAIRCASE VIA ROUTING FOR MEMORY (17893718)
Main Inventor
Shuangqiang Luo
METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS (17898107)
Main Inventor
Martin J. Barclay
SEMICONDUCTOR DEVICE ASSEMBLIES WITH COPLANAR INTERCONNECT STRUCTURES, AND METHODS FOR MAKING THE SAME (17899586)
Main Inventor
Thiagarajan Raman
MICROELECTRONIC DEVICES INCLUDING STADIUM STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS (17822421)
Main Inventor
Lifang Xu
METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS (17823472)
Main Inventor
Mohad Baboli
METHODS OF FORMING MICROELECTRONIC DEVICES INCLUDING STAIR STEP STRUCTURES (18504901)
Main Inventor
Harsh Narendrakumar Jain
Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells (17900064)
Main Inventor
Tom George
Memory Circuitry And Method Used In Forming Memory Circuitry (17944343)
Main Inventor
Jivaan Kishore Jhothiraman
SEMICONDUCTOR DEVICE ASSEMBLY SUBSTRATES WITH TUNNELED INTERCONNECTS, AND METHODS FOR MAKING THE SAME (17893968)
Main Inventor
Yun Ting Hsu
MEMORY ARRAY STRUCTURES AND METHODS OF THEIR FABRICATION (17961025)
Main Inventor
Shyam Surthi
SEMICONDUCTOR DEVICE INTERCONNECTS FORMED THROUGH VOLUMETRIC EXPANSION (18199741)
Main Inventor
Kyle K. Kirby
SEMICONDUCTOR DIE STACKS AND ASSOCIATED SYSTEMS AND METHODS (18220734)
Main Inventor
Kyle K. Kirby
SEMICONDUCTOR DEVICE WITH VOLUMETRICALLY-EXPANDED SIDE-CONNECTED INTERCONNECTS (18237225)
Main Inventor
Kyle K. Kirby
SEMICONDUCTOR CONDUCTIVE PILLAR DEVICE AND METHOD (17823162)
Main Inventor
Hidenori Yamaguchi
SOLDER BASED HYBRID BONDING FOR FINE PITCH AND THIN BLT INTERCONNECTION (18502389)
Main Inventor
Wei Zhou
SUBSTRATES WITH SPACERS, INCLUDING SUBSTRATES WITH SOLDER RESIST SPACERS, AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS (17899522)
Main Inventor
Bong Woo Choi
SEMICONDUCTOR DEVICE WITH A POLYMER LAYER (17899574)
Main Inventor
Wei Zhou
DIE EDGE FILLET AND 3D-PRINTED CNT AS BENDING STRESS BUFFER (17823189)
Main Inventor
Chen Yu Huang
SEMICONDUCTOR DEVICE ASSEMBLIES WITH BALANCED WIRES, AND ASSOCIATED METHODS (17898368)
Main Inventor
Chin Hui Chong
WIRE BONDING DIRECTLY ON EXPOSED CONDUCTIVE VIAS AND INTERCONNECTS AND RELATED SYSTEMS AND METHODS (17899550)
Main Inventor
Kelvin Tan Aik Boo
PIEZOELECTRIC MATERIALS FOR ON-DIE THERMAL ENHANCEMENT OF HYBRID BONDING AND ASSOCIATED SYSTEMS AND METHODS (17898330)
Main Inventor
Byung Hoon Moon
EMBEDDED NANOPARTICLES FOR ON-DIE THERMAL ENHANCEMENT OF HYBRID BONDING AND ASSOCIATED SYSTEMS AND METHODS (17898356)
Main Inventor
Bang-Ning Hsu
SEMICONDUCTOR DEVICE CIRCUITRY FORMED FROM REMOTE RESERVOIRS (18237202)
Main Inventor
Kyle K. Kirby
EXTENDED BOND PAD FOR SEMICONDUCTOR DEVICE ASSEMBLIES (17896030)
Main Inventor
Kelvin Tan Aik Boo
SEMICONDUCTOR DEVICES, ASSEMBLIES, AND ASSOCIATED METHODS (17893941)
Main Inventor
Raj K. Bansal
SEMICONDUCTOR DEVICE WITH CIRCUIT COMPONENTS FORMED THROUGH INTER-DIE CONNECTIONS (18237259)
Main Inventor
Kyle K. Kirby
STACKED CAPACITORS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED SYSTEMS AND METHODS (17899592)
Main Inventor
Seng Kim Ye
MODULAR SYSTEMS IN PACKAGES, AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS (17897156)
Main Inventor
Kelvin Tan Aik Boo
APPARATUS INCLUDING ADJUSTED WELLS AND METHODS OF MANUFACTURING THE SAME (17898184)
Main Inventor
Michael A. Smith
CONTACT ARRANGEMENTS FOR TRANSISTORS (18234129)
Main Inventor
Yoshikazu Moriwaki
TRANSISTORS WITH MITIGATED FREE BODY EFFECT (18237206)
Main Inventor
Kamal M. Karda
SYSTEMS AND TECHNIQUES FOR TIMING MISMATCH REDUCTION (17895826)
Main Inventor
Yoshihito Morishita
CLOUD STORAGE WITH ENHANCED DATA PRIVACY (17898382)
Main Inventor
Zhan Liu
SECURELY SHARING DATA AND ACCESS PERMISSIONS IN A CLOUD ENVIRONMENT (17899177)
Main Inventor
Zhan Liu
GENERATING A SHARED SECRET FOR AN ELECTRONIC SYSTEM (18221790)
Main Inventor
Lance W. Dover
GROUP DIGITAL CERTIFICATES FOR DEVICE ONBOARDING (17895975)
Main Inventor
Zhan Liu
SEMICONDUCTOR PACKAGING WITH REDUCED STANDOFF HEIGHT (17894070)
Main Inventor
Ling Pan
SUBSTRATES WITH CONTINUOUS SLOT VIAS (17899477)
Main Inventor
Walter L. Moden
INTEGRATED BRACKET FOR ENHANCED HEAT DISSIPATION (18239427)
Main Inventor
Shiva Pahwa
COMPACT MICROELECTRONIC 6T SRAM MEMORY DEVICES, AND RELATED SYSTEMS AND METHODS (17898060)
Main Inventor
Mitsunari Sukekawa
MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SEPARATE READ AND WRITE DATA LINES (18238269)
Main Inventor
Durai Vishak Nirmal Ramaswamy
FABRICATION METHOD OF A LATERAL 3D MEMORY DEVICE (17895017)
Main Inventor
Yoshitaka Nakamura
MICROELECTRONIC DEVICES, RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS (17898233)
Main Inventor
Fatma Arzum Simsek-Ege
BOTTOM ELECTRODE CONTACT FOR A VERTICAL THREE-DIMENSIONAL MEMORY (18387641)
Main Inventor
Yuichi Yokoyama
CONDUCTIVE STRUCTURES (17896039)
Main Inventor
Daniel Billingsley
SHALLOW TRENCH ISOLATION RECESS CONTROL (18234145)
Main Inventor
Chunhua Yao
SACRIFICIAL POLYSILICON IN INTEGRATION OF MEMORY ARRAY WITH PERIPHERY (18236544)
Main Inventor
Shivani Srivastava
INTEGRATION OF MEMORY ARRAY WITH PERIPHERY (18236566)
Main Inventor
Shivani Srivastava
MEMORY ARRAY - PERIPHERY INTEGRATION WITH SPLIT BARRIER METAL STACK (18236579)
Main Inventor
Russell Allen Benson
METAL SILICIDE IN INTEGRATION OF MEMORY ARRAY WITH PERIPHERY (18236556)
Main Inventor
Shivani Srivastava
MEMORY DEVICES HAVING ONE-TIME-PROGRAMMABLE FUSES AND/OR ANTIFUSES FORMED FROM THIN-FILM TRANSISTORS (17898232)
Main Inventor
Paolo Fantini
MICROELECTRONIC DEVICES WITH A TIERED STACK OF CONDUCTIVE, INSULATIVE, AND PARTIALLY-SACRIFICIAL STRUCTURES, AND RELATED SYSTEMS AND METHODS (17822101)
Main Inventor
David H. Wells
ELECTRONIC DEVICES COMPRISING BLOCKING REGIONS, AND RELATED ELECTRONIC SYSTEMS AND METHODS (17823276)
Main Inventor
John D. Hopkins
Memory Circuitry And Method Used In Forming Memory Circuitry (17897399)
Main Inventor
John D. Hopkins
Memory Circuitry And Method Used In Forming Memory Circuitry (17897516)
Main Inventor
John D. Hopkins
ELECTRONIC DEVICES COMPRISING A STEPPED PILLAR REGION, AND RELATED METHODS (17897976)
Main Inventor
Masaaki Higuchi
MEMORY DEVICE INCLUDING STAIRCASE STRUCTURES AND ADJACENT TRENCH STRUCTURES (18237661)
Main Inventor
Shruthi Kumara Vadivel
Memory Circuitry And Method Used In Forming Memory Circuitry (17893436)
Main Inventor
Matthew J. King
Memory Circuitry And Method Used In Forming Memory Circuitry (17897350)
Main Inventor
John D. Hopkins
MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND MEMORY ELEMENT BETWEEN CHANNEL REGION AND CONDUCTIVE PLATE (18238291)
Main Inventor
Kamal M. Karda
Integrated Assemblies Comprising Hydrogen Diffused Within Two or More Different Semiconductor Materials, and Methods of Forming Integrated Assemblies (18387921)
Main Inventor
Kamal M. Karda
