17823468. QUEUEING ASYNCHRONOUS EVENTS FOR ACCEPTANCE BY THREADS EXECUTING IN A BARREL PROCESSOR simplified abstract (Micron Technology, Inc.)
QUEUEING ASYNCHRONOUS EVENTS FOR ACCEPTANCE BY THREADS EXECUTING IN A BARREL PROCESSOR
Organization Name
Inventor(s)
Christopher Baronne of Allen TX (US)
Tony M. Brewer of Plano TX (US)
QUEUEING ASYNCHRONOUS EVENTS FOR ACCEPTANCE BY THREADS EXECUTING IN A BARREL PROCESSOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 17823468 titled 'QUEUEING ASYNCHRONOUS EVENTS FOR ACCEPTANCE BY THREADS EXECUTING IN A BARREL PROCESSOR
Simplified Explanation
- A barrel multithreaded processor includes an asynchronous event handler to manage thread creation instructions. - The event handler determines the size of return values from the thread creation instruction. - It checks if there is enough memory space to store the return values. - If there is sufficient space, it allocates memory to store the return parameters. - The handler provides access to the return values to the parent thread based on a thread return instruction from the child thread.
Potential Applications
This technology could be applied in: - Multithreaded processors - Systems requiring efficient event message handling
Problems Solved
- Efficient handling of asynchronous events in a processor - Managing return values from child threads in a multithreaded environment
Benefits
- Improved performance in handling event messages - Efficient memory allocation for return values - Seamless communication between parent and child threads
Original Abstract Submitted
Devices and techniques for asynchronous event message handing in a processor are described herein. A barrel multithreaded processor may include an asynchronous event handler to receive an indication of a thread create instruction from a parent thread, determine a return value size of return values from the indication of the thread create instruction, determine whether sufficient space exists in the memory to store the return values, allocate space in the memory to store the return parameters in response to determining that there is sufficient space in the memory to store the return values, and provide access to the return values from the allocated space to the parent thread based at least in part on a thread return instruction from the child thread.
