17821924. SINGLE-BIT ERROR INDICATION FOR A MEMORY BUILT-IN SELF-TEST simplified abstract (Micron Technology, Inc.)
SINGLE-BIT ERROR INDICATION FOR A MEMORY BUILT-IN SELF-TEST
Organization Name
Inventor(s)
Scott E. Schaefer of Boise ID (US)
SINGLE-BIT ERROR INDICATION FOR A MEMORY BUILT-IN SELF-TEST - A simplified explanation of the abstract
This abstract first appeared for US patent application 17821924 titled 'SINGLE-BIT ERROR INDICATION FOR A MEMORY BUILT-IN SELF-TEST
Simplified Explanation
The patent application describes a method for single-bit error indication in a memory built-in self-test.
- Memory device reads bits stored in a mode register for memory built-in self-test.
- Memory device performs self-test on memory sections based on the read bits.
- Memory device identifies single-bit errors in memory sections during self-test.
- Memory device transmits indication of number of single-bit errors after repairing them.
Potential Applications
- Computer memory testing
- Embedded systems testing
- Quality control in memory manufacturing
Problems Solved
- Efficient detection of single-bit errors in memory
- Streamlined memory testing process
- Improved reliability of memory devices
Benefits
- Early detection of errors
- Reduced downtime for memory maintenance
- Enhanced overall performance of memory devices
Original Abstract Submitted
Implementations described herein relate to single-bit error indication for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may perform the memory built-in self-test for one or more memory sections of the memory device based on reading the one or more bits that are stored in the mode register of the memory device. The memory device may identify a number of single-bit errors associated with the one or more memory sections of the memory device based on performing the memory built-in self-test. The memory device may transmit an indication of the number of single-bit errors based on repairing one or more of the single-bit errors associated with the one or more memory sections of the memory device.
