Category:Joydeep Ray of Folsom CA (US)
Joydeep Ray of Folsom CA (US)
Executive Summary
Joydeep Ray of Folsom CA (US) is an inventor who has filed 7 patents. Their primary areas of innovation include Processor architectures; Processor configuration, e.g. pipelining (5 patents), {from multiple instruction streams, e.g. multistreaming} (4 patents), {controlled by a single instruction for multiple threads [SIMT] in parallel} (4 patents), and they have worked with companies such as Intel Corporation (7 patents). Their most frequent collaborators include (6 collaborations), (6 collaborations), (4 collaborations).
Patent Filing Activity
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Technology Areas
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List of Technology Areas
- G06T1/20 (Processor architectures; Processor configuration, e.g. pipelining): 5 patents
- G06F9/3851 ({from multiple instruction streams, e.g. multistreaming}): 4 patents
- G06F9/3888 ({controlled by a single instruction for multiple threads [SIMT] in parallel}): 4 patents
- G06T1/60 (Memory management): 3 patents
- G06F9/3001 ({Arithmetic instructions}): 3 patents
- G06F9/30014 ({with variable precision}): 3 patents
- G06T15/005 ({General purpose rendering architectures}): 3 patents
- G06F9/4843 (Program initiating; Program switching, e.g. by interrupt): 2 patents
- G06F12/0866 (for peripheral storage systems, e.g. disk cache): 2 patents
- G06F12/0897 (in hierarchically structured memory systems, e.g. virtual memory systems): 2 patents
- G06F7/5443 (for evaluating functions by calculation {(): 2 patents
- G06F9/30036 ({Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}): 2 patents
- G06F9/3887 ({controlled by a single instruction for multiple data lanes [SIMD]}): 2 patents
- G06F17/16 (Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition): 2 patents
- G06N3/08 (Learning methods): 2 patents
- G06N3/044 (Recurrent networks, e.g. Hopfield networks): 2 patents
- G06N3/045 (Combinations of networks): 2 patents
- G06N3/063 (using electronic means): 2 patents
- G06F9/46 (Multiprogramming arrangements): 1 patents
- G06F9/4881 (Program initiating; Program switching, e.g. by interrupt): 1 patents
- G06F9/5027 (Allocation of resources, e.g. of the central processing unit [CPU]): 1 patents
- G06F9/522 (Program synchronisation; Mutual exclusion, e.g. by means of semaphores): 1 patents
- G06F9/545 (Interprogram communication): 1 patents
- G06F12/0842 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
- G06F15/16 (Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs {(coordinating program control therefor): 1 patents
- G06F15/76 (Architectures of general purpose stored program computers (with program plugboard): 1 patents
- G06F2209/5018 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06T2200/28 (IMAGE DATA PROCESSING OR GENERATION, IN GENERAL): 1 patents
- G06T15/503 ({Blending, e.g. for anti-aliasing}): 1 patents
- G06T11/203 ({Drawing of straight lines or curves}): 1 patents
- G06T11/40 (Filling a planar surface by adding surface attributes, e.g. colour or texture): 1 patents
- G06T15/80 (Shading): 1 patents
- G06T2200/12 (IMAGE DATA PROCESSING OR GENERATION, IN GENERAL): 1 patents
- G06F15/7839 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F7/575 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F7/588 (Random or pseudo-random number generators): 1 patents
- G06F9/3004 ({to perform operations on memory}): 1 patents
- G06F9/30043 ({LOAD or STORE instructions; Clear instruction}): 1 patents
- G06F9/30047 ({Prefetch instructions; cache control instructions}): 1 patents
- G06F9/30065 ({Loop control instructions; iterative instructions, e.g. LOOP, REPEAT}): 1 patents
- G06F9/30079 ({Pipeline control instructions, e.g. multicycle NOP}): 1 patents
- G06F9/5011 (Allocation of resources, e.g. of the central processing unit [CPU]): 1 patents
- G06F9/5077 (Allocation of resources, e.g. of the central processing unit [CPU]): 1 patents
- G06F12/0215 ({with look ahead addressing means}): 1 patents
- G06F12/0238 ({Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}): 1 patents
- G06F12/0246 ({in block erasable memory, e.g. flash memory}): 1 patents
- G06F12/0607 (Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (): 1 patents
- G06F12/0802 (Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches): 1 patents
- G06F12/0804 (with main memory updating (): 1 patents
- G06F12/0811 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
- G06F12/0862 (with prefetch): 1 patents
- G06F12/0871 (Allocation or management of cache space): 1 patents
- G06F12/0875 (with dedicated cache, e.g. instruction or stack): 1 patents
- G06F12/0882 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
- G06F12/0891 (using clearing, invalidating or resetting means): 1 patents
- G06F12/0893 (Caches characterised by their organisation or structure): 1 patents
- G06F12/0895 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
- G06F12/1009 (Address translation): 1 patents
- G06F12/128 (Replacement control): 1 patents
- G06F15/8046 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F17/18 (for evaluating statistical data {, e.g. average values, frequency distributions, probability functions, regression analysis (forecasting specially adapted for a specific administrative, business or logistic context): 1 patents
- H03M7/46 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
- G06F9/3802 ({Instruction prefetching}): 1 patents
- G06F9/3818 ({Decoding for concurrent execution}): 1 patents
- G06F9/3867 ({using instruction pipelines}): 1 patents
- G06F2212/1021 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F2212/1044 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F2212/302 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F2212/401 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F2212/455 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F2212/60 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06T15/06 (Ray-tracing): 1 patents
- G06F3/14 (Digital output to display device {; Cooperation and interconnection of the display device with other functional units}): 1 patents
- G06F9/3017 ({Runtime instruction translation, e.g. macros}): 1 patents
- G06F9/3895 ({for complex operations, e.g. multidimensional or interleaved address generators, macros}): 1 patents
- G06N3/084 (Backpropagation, e.g. using gradient descent): 1 patents
- G09G5/363 (ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays): 1 patents
- G06T15/04 (Texture mapping): 1 patents
- G09G2360/06 (ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays): 1 patents
- G09G2360/08 (ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays): 1 patents
- G09G2360/121 (ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays): 1 patents
- G06F7/483 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G09G5/393 (ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays): 1 patents
- G06F1/16 (Constructional details or arrangements): 1 patents
- G06F9/30025 ({Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion}): 1 patents
- G06F9/3013 ({according to data content, e.g. floating-point registers, address registers}): 1 patents
- G06F2207/3824 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06N20/00 (Machine learning): 1 patents
- G06F9/3009 ({Thread control instructions}): 1 patents
- G06F9/30185 ({according to one or more bits in the instruction, e.g. prefix, sub-opcode}): 1 patents
- G06F9/461 (Multiprogramming arrangements): 1 patents
- G06T2200/04 (IMAGE DATA PROCESSING OR GENERATION, IN GENERAL): 1 patents
Companies
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List of Companies
- Intel Corporation: 7 patents
Collaborators
- Abhishek R. Appu of El Dorado Hills CA (US) (6 collaborations)
- Altug Koker of El Dorado Hills CA (US) (6 collaborations)
- Balaji Vembu of Folsom CA (US) (4 collaborations)
- Prasoonkumar Surti of Folsom CA (US) (3 collaborations)
- Vasanth Ranganathan of El Dorado Hills CA (US) (2 collaborations)
- Kamal Sinha of Rancho Cordova CA (US) (2 collaborations)
- David Puffer of Tempe AZ (US) (2 collaborations)
- Ping T. Tang of Edison NJ (US) (2 collaborations)
- Michael S. Strickland of Sunnyvale CA (US) (2 collaborations)
- Xiaoming Chen (2 collaborations)
- Anbang Yao (2 collaborations)
- Tatiana Shpeisman of Menlo Park CA (US) (2 collaborations)
- Aravindh Anantaraman of Folsom CA (US) (1 collaborations)
- Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) (1 collaborations)
- Valentin Andrei of San Jose CA (US) (1 collaborations)
- Nicolas Galoppo Von Borries of Portland OR (US) (1 collaborations)
- Varghese George of Folsom CA (US) (1 collaborations)
- Mike Macpherson of Portland OR (US) (1 collaborations)
- Subramaniam Maiyuran of Gold River CA (US) (1 collaborations)
- Lakshminarayana Striramassarma of Folsom CA (US) (1 collaborations)
- Scott Janus of Loomis CA (US) (1 collaborations)
- Brent Insko of Portland OR (US) (1 collaborations)
- Arthur Hunter of Cameron Park CA (US) (1 collaborations)
- James Valerio of North Plains OR (US) (1 collaborations)
- Ankur N. Shah of Folsom CA (US) (1 collaborations)
- Linda L. Hurd of Cool CA (US) (1 collaborations)
- Dukhwan Kim of San Jose CA (US) (1 collaborations)
- Mike B. Macpherson of Portland OR (US) (1 collaborations)
- John C. Weast of Portland OR (US) (1 collaborations)
- Feng Chen (1 collaborations)
- Farshad Akhbari of Chandler AZ (US) (1 collaborations)
- Narayan Srinivasa of Portland OR (US) (1 collaborations)
- Nadathur Rajagopalan Satish of Santa Clara CA (US) (1 collaborations)
- Himanshu Kaul of Portland OR (US) (1 collaborations)
- Mark A. Anders of Hillsboro OR (US) (1 collaborations)
- Sanu K. Mathew of Hillsboro OR (US) (1 collaborations)
- Nicolas C. Galoppo Von Borries of Portland OR (US) (1 collaborations)
- Eriko Nurvitadhi of Hillsboro OR (US) (1 collaborations)
- Rajkishore Barik of Santa Clara CA (US) (1 collaborations)
- Tsung-Han Lin of Campbell CA (US) (1 collaborations)
- Sanjeev Jahagirdar of Folsom CA (US) (1 collaborations)
- Ingo Wald of Salt Lake City UT (US) (1 collaborations)
- Subramaniam M. Maiyuran of Gold River CA (US) (1 collaborations)
- Guei-Yuan Lueh of San Jose CA (US) (1 collaborations)
- Murali Ramadoss of Folsom CA (US) (1 collaborations)
Subcategories
This category has the following 9 subcategories, out of 9 total.
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Pages in category "Joydeep Ray of Folsom CA (US)"
The following 68 pages are in this category, out of 68 total.
1
- 17884755. CONCURRENT COMPUTE CONTEXT simplified abstract (Intel Corporation)
- 17944500. OFFSET SCALING IN LOAD/STORE MESSAGES simplified abstract (Intel Corporation)
- 17944542. MERGING ATOMICS TO THE SAME CACHE LINE simplified abstract (Intel Corporation)
- 17949904. BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES simplified abstract (Intel Corporation)
- 17958216. SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING simplified abstract (Intel Corporation)
- 17959374. Regional Adjustment of Render Rate simplified abstract (Intel Corporation)
- 17971290. VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES simplified abstract (Intel Corporation)
- 17973203. BROADCAST ASYNCHRONOUS LOADS TO SHARED LOCAL MEMORY simplified abstract (Intel Corporation)
- 17987185. INCREASING PROCESSING RESOURCES IN PROCESSING CORES OF A GRAPHICS ENVIRONMENT simplified abstract (Intel Corporation)
- 18086441. LOAD STORE MICROARCHITECTURE CACHE ENHANCEMENTS simplified abstract (Intel Corporation)
- 18170808. LOAD STORE CACHE MICROARCHITECTURE simplified abstract (Intel Corporation)
- 18339827. PROCESSOR POWER MANAGEMENT simplified abstract (Intel Corporation)
- 18365595. SCHEDULING OF THREADS FOR EXECUTION UTILIZING LOAD BALANCING OF THREAD GROUPS simplified abstract (Intel Corporation)
- 18405933. SECTOR CACHE FOR COMPRESSION simplified abstract (Intel Corporation)
- 18436522. FRAGMENT COMPRESSION FOR COARSE PIXEL SHADING simplified abstract (Intel Corporation)
- 18456235. COMPUTE OPTIMIZATIONS FOR LOW PRECISION MACHINE LEARNING OPERATIONS simplified abstract (Intel Corporation)
- 18474361. Regional Adjustment of Render Rate simplified abstract (Intel Corporation)
- 18491474. INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES simplified abstract (Intel Corporation)
- 18511074. MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT simplified abstract (Intel Corporation)
- 18516716. SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU CONFIGURATION simplified abstract (Intel Corporation)
- 18517862. AUGMENTED REALITY VIRTUAL REALITY RAY TRACING SENSORY ENHANCEMENT SYSTEM, APPARATUS AND METHOD simplified abstract (Intel Corporation)
- 18532245. ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY simplified abstract (Intel Corporation)
- 18536581. APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSING ARCHITECTURE simplified abstract (Intel Corporation)
- 18587761. APPARATUS AND METHOD FOR THROTTLING A RAY TRACING PIPELINE simplified abstract (Intel Corporation)
- 18595649. BARRIERS AND SYNCHRONIZATION FOR MACHINE LEARNING AT AUTONOMOUS MACHINES simplified abstract (Intel Corporation)
- 18620284. MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS simplified abstract (Intel Corporation)
- 18626775. Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page Migration simplified abstract (Intel Corporation)
- 18773094. COMPUTE OPTIMIZATION MECHANISM (Intel Corporation)
- 18793247. MULTI-TILE MEMORY MANAGEMENT (Intel Corporation)
- 18822815. SCALAR CORE INTEGRATION (Intel Corporation)
I
- Intel corporation (20240112295). SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING simplified abstract
- Intel corporation (20240134527). VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES simplified abstract
- Intel corporation (20240134797). BROADCAST ASYNCHRONOUS LOADS TO SHARED LOCAL MEMORY simplified abstract
- Intel corporation (20240160478). INCREASING PROCESSING RESOURCES IN PROCESSING CORES OF A GRAPHICS ENVIRONMENT simplified abstract
- Intel corporation (20240161226). MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT simplified abstract
- Intel corporation (20240161227). ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY simplified abstract
- Intel corporation (20240163631). AUGMENTED REALITY VIRTUAL REALITY RAY TRACING SENSORY ENHANCEMENT SYSTEM, APPARATUS AND METHOD simplified abstract
- Intel corporation (20240177264). APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSING ARCHITECTURE simplified abstract
- Intel corporation (20240184572). INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING simplified abstract
- Intel corporation (20240184739). DYNAMIC MEMORY RECONFIGURATION simplified abstract
- Intel corporation (20240211403). LOAD STORE MICROARCHITECTURE CACHE ENHANCEMENTS simplified abstract
- Intel corporation (20240221295). FRAGMENT COMPRESSION FOR COARSE PIXEL SHADING simplified abstract
- Intel corporation (20240231621). VIRTUAL ADDRESS ACCESS TO GPU SURFACE AND SAMPLER STATES simplified abstract
- Intel corporation (20240232088). BROADCAST ASYNCHRONOUS LOADS TO SHARED LOCAL MEMORY simplified abstract
- Intel corporation (20240232094). SECTOR CACHE FOR COMPRESSION simplified abstract
- Intel corporation (20240256456). DATA PREFETCHING FOR GRAPHICS DATA PROCESSING simplified abstract
- Intel corporation (20240256483). GRAPHICS PROCESSOR DATA ACCESS AND SHARING simplified abstract
- Intel corporation (20240256825). CONVOLUTIONAL NEURAL NETWORK OPTIMIZATION MECHANISM simplified abstract
- Intel corporation (20240257294). COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS simplified abstract
- Intel corporation (20240264657). System, Apparatus And Method For Increasing Performance In A Processor During A Voltage Ramp simplified abstract
- Intel corporation (20240280987). BARRIERS AND SYNCHRONIZATION FOR MACHINE LEARNING AT AUTONOMOUS MACHINES simplified abstract
- Intel corporation (20240281249). LOAD STORE CACHE MICROARCHITECTURE simplified abstract
- Intel corporation (20240282042). APPARATUS AND METHOD FOR THROTTLING A RAY TRACING PIPELINE simplified abstract
- Intel corporation (20240320184). MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS simplified abstract
- Intel corporation (20240330001). BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES simplified abstract
- Intel corporation (20240345990). Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page Migration simplified abstract
- Intel corporation (20240353912). INTERCONNECT FABRIC LINK WIDTH REDUCTION TO REDUCE INSTANTANEOUS POWER CONSUMPTION simplified abstract
- Intel corporation (20240354043). Regional Adjustment of Render Rate simplified abstract
- Intel corporation (20240355032). GRAPHICS SYSTEM WITH ADDITIONAL CONTEXT simplified abstract
- Intel corporation (20240403259). COMPRESSION TECHNIQUES
- Intel corporation (20240403259). COMPRESSION TECHNIQUES simplified abstract
- Intel corporation (20240404487). GRAPHICS WITH ADAPTIVE TEMPORAL ADJUSTMENTS
- Intel corporation (20240404487). GRAPHICS WITH ADAPTIVE TEMPORAL ADJUSTMENTS simplified abstract
- Intel corporation (20240411717). CACHE STRUCTURE AND UTILIZATION
- Intel corporation (20240427842). MATRIX OPERATION OPTIMIZATION MECHANISM
- Intel corporation (20250068588). SCALAR CORE INTEGRATION
Categories:
- Abhishek R. Appu of El Dorado Hills CA (US)
- Altug Koker of El Dorado Hills CA (US)
- Balaji Vembu of Folsom CA (US)
- Prasoonkumar Surti of Folsom CA (US)
- Vasanth Ranganathan of El Dorado Hills CA (US)
- Kamal Sinha of Rancho Cordova CA (US)
- David Puffer of Tempe AZ (US)
- Ping T. Tang of Edison NJ (US)
- Michael S. Strickland of Sunnyvale CA (US)
- Xiaoming Chen
- Anbang Yao
- Tatiana Shpeisman of Menlo Park CA (US)
- Aravindh Anantaraman of Folsom CA (US)
- Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US)
- Valentin Andrei of San Jose CA (US)
- Nicolas Galoppo Von Borries of Portland OR (US)
- Varghese George of Folsom CA (US)
- Mike Macpherson of Portland OR (US)
- Subramaniam Maiyuran of Gold River CA (US)
- Lakshminarayana Striramassarma of Folsom CA (US)
- Scott Janus of Loomis CA (US)
- Brent Insko of Portland OR (US)
- Arthur Hunter of Cameron Park CA (US)
- James Valerio of North Plains OR (US)
- Ankur N. Shah of Folsom CA (US)
- Linda L. Hurd of Cool CA (US)
- Dukhwan Kim of San Jose CA (US)
- Mike B. Macpherson of Portland OR (US)
- John C. Weast of Portland OR (US)
- Feng Chen
- Farshad Akhbari of Chandler AZ (US)
- Narayan Srinivasa of Portland OR (US)
- Nadathur Rajagopalan Satish of Santa Clara CA (US)
- Himanshu Kaul of Portland OR (US)
- Mark A. Anders of Hillsboro OR (US)
- Sanu K. Mathew of Hillsboro OR (US)
- Nicolas C. Galoppo Von Borries of Portland OR (US)
- Eriko Nurvitadhi of Hillsboro OR (US)
- Rajkishore Barik of Santa Clara CA (US)
- Tsung-Han Lin of Campbell CA (US)
- Sanjeev Jahagirdar of Folsom CA (US)
- Ingo Wald of Salt Lake City UT (US)
- Subramaniam M. Maiyuran of Gold River CA (US)
- Guei-Yuan Lueh of San Jose CA (US)
- Murali Ramadoss of Folsom CA (US)
- Joydeep Ray of Folsom CA (US)
- Inventors
- Inventors filing patents with Intel Corporation