Category:Subramaniam Maiyuran of Gold River CA (US)
Subramaniam Maiyuran
Subramaniam Maiyuran from Gold River CA (US) has applied for patents in technology areas such as G06F15/80, G06F9/30, G06F9/38 with intel corporation.
Patents
Subcategories
This category has the following 8 subcategories, out of 8 total.
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Pages in category "Subramaniam Maiyuran of Gold River CA (US)"
The following 30 pages are in this category, out of 30 total.
1
- 17959374. Regional Adjustment of Render Rate simplified abstract (Intel Corporation)
- 18339454. DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS simplified abstract (Intel Corporation)
- 18426504. MECHANISM TO PERFORM SINGLE PRECISION FLOATING POINT EXTENDED MATH OPERATIONS simplified abstract (Intel Corporation)
- 18470553. INSTRUCTION PREFETCH MECHANISM simplified abstract (Intel Corporation)
- 18474361. Regional Adjustment of Render Rate simplified abstract (Intel Corporation)
- 18511074. MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT simplified abstract (Intel Corporation)
- 18516716. SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU CONFIGURATION simplified abstract (Intel Corporation)
- 18532245. ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY simplified abstract (Intel Corporation)
- 18621539. UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS simplified abstract (Intel Corporation)
- 18626775. Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page Migration simplified abstract (Intel Corporation)
- 18793247. MULTI-TILE MEMORY MANAGEMENT (Intel Corporation)
- 18822815. SCALAR CORE INTEGRATION (Intel Corporation)
I
- Intel corporation (20240103910). SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES simplified abstract
- Intel corporation (20240161226). MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT simplified abstract
- Intel corporation (20240161227). ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY simplified abstract
- Intel corporation (20240184739). DYNAMIC MEMORY RECONFIGURATION simplified abstract
- Intel corporation (20240241693). MECHANISM TO PERFORM SINGLE PRECISION FLOATING POINT EXTENDED MATH OPERATIONS simplified abstract
- Intel corporation (20240256274). SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCHITECTURE simplified abstract
- Intel corporation (20240256456). DATA PREFETCHING FOR GRAPHICS DATA PROCESSING simplified abstract
- Intel corporation (20240256483). GRAPHICS PROCESSOR DATA ACCESS AND SHARING simplified abstract
- Intel corporation (20240257294). COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS simplified abstract
- Intel corporation (20240320000). UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS simplified abstract
- Intel corporation (20240345990). Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page Migration simplified abstract
- Intel corporation (20240354043). Regional Adjustment of Render Rate simplified abstract
- Intel corporation (20240403044). NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SCALE INSTRUCTIONS WITHIN A GRAPHICS PROCESSING UNIT VIA REUSE OF FUSED MULTIPLY-ADD EXECUTION UNIT HARDWARE LOGIC
- Intel corporation (20240403044). NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SCALE INSTRUCTIONS WITHIN A GRAPHICS PROCESSING UNIT VIA REUSE OF FUSED MULTIPLY-ADD EXECUTION UNIT HARDWARE LOGIC simplified abstract
- Intel corporation (20240403259). COMPRESSION TECHNIQUES
- Intel corporation (20240403259). COMPRESSION TECHNIQUES simplified abstract
- Intel corporation (20240411717). CACHE STRUCTURE AND UTILIZATION
- Intel corporation (20250068588). SCALAR CORE INTEGRATION