Category:Prasoonkumar Surti of Folsom CA (US)
Prasoonkumar Surti of Folsom CA (US)
Executive Summary
Prasoonkumar Surti of Folsom CA (US) is an inventor who has filed 9 patents. Their primary areas of innovation include Processor architectures; Processor configuration, e.g. pipelining (7 patents), Memory management (6 patents), ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models (4 patents), and they have worked with companies such as Intel Corporation (8 patents), INTEL CORPORATION (1 patents). Their most frequent collaborators include (7 collaborations), (6 collaborations), (5 collaborations).
Patent Filing Activity
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Technology Areas
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List of Technology Areas
- G06T1/20 (Processor architectures; Processor configuration, e.g. pipelining): 7 patents
- G06T1/60 (Memory management): 6 patents
- G06F15/7839 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
- G06F7/5443 (for evaluating functions by calculation {(): 4 patents
- G06F7/575 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
- G06F7/588 (Random or pseudo-random number generators): 4 patents
- G06F9/3001 ({Arithmetic instructions}): 4 patents
- G06F9/30014 ({with variable precision}): 4 patents
- G06F9/30036 ({Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}): 4 patents
- G06F9/3004 ({to perform operations on memory}): 4 patents
- G06F9/30043 ({LOAD or STORE instructions; Clear instruction}): 4 patents
- G06F9/30047 ({Prefetch instructions; cache control instructions}): 4 patents
- G06F9/30079 ({Pipeline control instructions, e.g. multicycle NOP}): 4 patents
- G06F9/3887 ({controlled by a single instruction for multiple data lanes [SIMD]}): 4 patents
- G06F9/5011 (Allocation of resources, e.g. of the central processing unit [CPU]): 4 patents
- G06F9/5077 (Allocation of resources, e.g. of the central processing unit [CPU]): 4 patents
- G06F12/0215 ({with look ahead addressing means}): 4 patents
- G06F12/0238 ({Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}): 4 patents
- G06F12/0246 ({in block erasable memory, e.g. flash memory}): 4 patents
- G06F12/0607 (Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (): 4 patents
- G06F12/0802 (Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches): 4 patents
- G06F12/0804 (with main memory updating (): 4 patents
- G06F12/0811 (in hierarchically structured memory systems, e.g. virtual memory systems): 4 patents
- G06F12/0862 (with prefetch): 4 patents
- G06F12/0866 (for peripheral storage systems, e.g. disk cache): 4 patents
- G06F12/0871 (Allocation or management of cache space): 4 patents
- G06F12/0875 (with dedicated cache, e.g. instruction or stack): 4 patents
- G06F12/0882 (in hierarchically structured memory systems, e.g. virtual memory systems): 4 patents
- G06F12/0891 (using clearing, invalidating or resetting means): 4 patents
- G06F12/0893 (Caches characterised by their organisation or structure): 4 patents
- G06F12/0895 (in hierarchically structured memory systems, e.g. virtual memory systems): 4 patents
- G06F12/0897 (in hierarchically structured memory systems, e.g. virtual memory systems): 4 patents
- G06F12/1009 (Address translation): 4 patents
- G06F12/128 (Replacement control): 4 patents
- G06F15/8046 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
- G06F17/16 (Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition): 4 patents
- G06F17/18 (for evaluating statistical data {, e.g. average values, frequency distributions, probability functions, regression analysis (forecasting specially adapted for a specific administrative, business or logistic context): 4 patents
- H03M7/46 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 4 patents
- G06F9/3802 ({Instruction prefetching}): 4 patents
- G06F9/3818 ({Decoding for concurrent execution}): 4 patents
- G06F9/3867 ({using instruction pipelines}): 4 patents
- G06F2212/1021 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
- G06F2212/1044 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
- G06F2212/302 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
- G06F2212/401 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
- G06F2212/455 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
- G06F2212/60 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
- G06N3/08 (Learning methods): 4 patents
- G06F9/3888 ({controlled by a single instruction for multiple threads [SIMT] in parallel}): 4 patents
- G06F9/30065 ({Loop control instructions; iterative instructions, e.g. LOOP, REPEAT}): 3 patents
- G06T15/06 (Ray-tracing): 3 patents
- G06F12/0888 (using selective caching, e.g. bypass): 3 patents
- G06F2212/1008 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 3 patents
- G06T11/40 (Filling a planar surface by adding surface attributes, e.g. colour or texture): 2 patents
- G06T2200/12 (IMAGE DATA PROCESSING OR GENERATION, IN GENERAL): 2 patents
- G06T15/005 ({General purpose rendering architectures}): 2 patents
- G06F16/2237 ({Vectors, bitmaps or matrices}): 1 patents
- G06N20/00 (Machine learning): 1 patents
- G06T15/503 ({Blending, e.g. for anti-aliasing}): 1 patents
- G06T11/203 ({Drawing of straight lines or curves}): 1 patents
- G06T15/80 (Shading): 1 patents
- G06T17/20 (Finite element generation, e.g. wire-frame surface description, {tesselation}): 1 patents
- G06F9/3009 ({Thread control instructions}): 1 patents
- G06F9/30185 ({according to one or more bits in the instruction, e.g. prefix, sub-opcode}): 1 patents
- G06F9/3851 ({from multiple instruction streams, e.g. multistreaming}): 1 patents
- G06F9/461 (Multiprogramming arrangements): 1 patents
- G06F9/4843 (Program initiating; Program switching, e.g. by interrupt): 1 patents
Companies
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List of Companies
- Intel Corporation: 8 patents
- INTEL CORPORATION: 1 patents
Collaborators
- Joydeep Ray of Folsom CA (US) (7 collaborations)
- Abhishek R. Appu of El Dorado Hills CA (US) (6 collaborations)
- Altug Koker of El Dorado Hills CA (US) (5 collaborations)
- Vasanth Ranganathan of El Dorado Hills CA (US) (5 collaborations)
- Valentin Andrei of San Jose CA (US) (4 collaborations)
- Varghese George of Folsom CA (US) (4 collaborations)
- Subramaniam Maiyuran of Gold River CA (US) (4 collaborations)
- Lakshminarayanan Striramassarma of Folsom CA (US) (4 collaborations)
- Aravindh Anantaraman of Folsom CA (US) (3 collaborations)
- Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) (3 collaborations)
- Mike Macpherson of Portland OR (US) (3 collaborations)
- Scott Janus of Loomis CA (US) (3 collaborations)
- Brent Insko of Portland OR (US) (3 collaborations)
- Nicolas Galoppo Von Borries of Portland OR (US) (2 collaborations)
- Kamal Sinha of Rancho Cordova CA (US) (2 collaborations)
- Arthur Hunter of Cameron Park CA (US) (2 collaborations)
- David Puffer of Tempe AZ (US) (2 collaborations)
- Murali Ramadoss of Folsom CA (US) (2 collaborations)
- Pattabhiraman K (2 collaborations)
- Abhishek Appu of El Dorado Hills CA (US) (2 collaborations)
- Karol Szerszen of Hillsboro OR (US) (1 collaborations)
- Eric Liskay of Folsom CA (US) (1 collaborations)
- Karthik Vaidyanathan of San Francisco CA (US) (1 collaborations)
- Lakshminarayana Striramassarma of Folsom CA (US) (1 collaborations)
- James Valerio of North Plains OR (US) (1 collaborations)
- Ankur N. Shah of Folsom CA (US) (1 collaborations)
- Ingo Wald of Salt Lake City UT (US) (1 collaborations)
- Subramaniam M. Maiyuran of Gold River CA (US) (1 collaborations)
- Balaji Vembu of Folsom CA (US) (1 collaborations)
- Guei-Yuan Lueh of San Jose CA (US) (1 collaborations)
- Sean Coleman of Folsom CA (US) (1 collaborations)
- Mike MacPherson of Portland OR (US) (1 collaborations)
- ElMoustapha Ould-Ahmed-Vall of Chandler AZ (US) (1 collaborations)
- Jayakrishna P S (1 collaborations)
- SungYe Kim of Folsom CA (US) (1 collaborations)
- Ben Ashbaugh of Folsom CA (US) (1 collaborations)
- Jonathan Pearce of Hillsboro OR (US) (1 collaborations)
- Yoav Harel of Carmichael CA (US) (1 collaborations)
- Arthur Hunter, JR. of Cameron Park CA (US) (1 collaborations)
- Marian Alin Petre of San Mateo CA (US) (1 collaborations)
- Shailesh Shah of Folsom CA (US) (1 collaborations)
- Kamal Sinha of Folsom CA (US) (1 collaborations)
- Vikranth Vemulapalli of Folsom CA (US) (1 collaborations)
- Michael J. Norris of Folsom CA (US) (1 collaborations)
Subcategories
This category has the following 7 subcategories, out of 7 total.
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Pages in category "Prasoonkumar Surti of Folsom CA (US)"
The following 36 pages are in this category, out of 36 total.
1
- 18339454. DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS simplified abstract (Intel Corporation)
- 18339827. PROCESSOR POWER MANAGEMENT simplified abstract (Intel Corporation)
- 18405933. SECTOR CACHE FOR COMPRESSION simplified abstract (Intel Corporation)
- 18413252. VIRTUAL REALITY APPARATUS AND METHOD INCLUDING PRIORITIZED PIXEL SHADER OPERATIONS, ALTERNATE EYE RENDERING, AND/OR AUGMENTED TIMEWARP simplified abstract (Intel Corporation)
- 18413286. APPARATUS AND METHOD FOR A HIERARCHICAL BEAM TRACER simplified abstract (Intel Corporation)
- 18436522. FRAGMENT COMPRESSION FOR COARSE PIXEL SHADING simplified abstract (Intel Corporation)
- 18492520. Lossless Compression for Multisample Render Targets Alongside Fragment Compression simplified abstract (Intel Corporation)
- 18517318. CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER simplified abstract (Intel Corporation)
- 18517862. AUGMENTED REALITY VIRTUAL REALITY RAY TRACING SENSORY ENHANCEMENT SYSTEM, APPARATUS AND METHOD simplified abstract (Intel Corporation)
- 18587761. APPARATUS AND METHOD FOR THROTTLING A RAY TRACING PIPELINE simplified abstract (Intel Corporation)
- 18589239. APPARATUS AND METHOD USING TRIANGLE PAIRS AND SHARED TRANSFORMATION CIRCUITRY TO IMPROVE RAY TRACING PERFORMANCE simplified abstract (Intel Corporation)
- 18620284. MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS simplified abstract (Intel Corporation)
- 18626775. Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page Migration simplified abstract (Intel Corporation)
- 18793247. MULTI-TILE MEMORY MANAGEMENT (Intel Corporation)
I
- Intel corporation (20240104825). APPARATUS AND METHOD FOR QUANTIZED CONVERGENT DIRECTION-BASED RAY SORTING simplified abstract
- Intel corporation (20240129503). Lossless Compression for Multisample Render Targets Alongside Fragment Compression simplified abstract
- Intel corporation (20240161356). CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER simplified abstract
- Intel corporation (20240163631). AUGMENTED REALITY VIRTUAL REALITY RAY TRACING SENSORY ENHANCEMENT SYSTEM, APPARATUS AND METHOD simplified abstract
- Intel corporation (20240184739). DYNAMIC MEMORY RECONFIGURATION simplified abstract
- Intel corporation (20240221295). FRAGMENT COMPRESSION FOR COARSE PIXEL SHADING simplified abstract
- Intel corporation (20240232094). SECTOR CACHE FOR COMPRESSION simplified abstract
- Intel corporation (20240233244). APPARATUS AND METHOD FOR A HIERARCHICAL BEAM TRACER simplified abstract
- Intel corporation (20240233250). VIRTUAL REALITY APPARATUS AND METHOD INCLUDING PRIORITIZED PIXEL SHADER OPERATIONS, ALTERNATE EYE RENDERING, AND/OR AUGMENTED TIMEWARP simplified abstract
- Intel corporation (20240256456). DATA PREFETCHING FOR GRAPHICS DATA PROCESSING simplified abstract
- Intel corporation (20240256483). GRAPHICS PROCESSOR DATA ACCESS AND SHARING simplified abstract
- Intel corporation (20240257294). COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS simplified abstract
- Intel corporation (20240257433). APPARATUS AND METHOD FOR ASYNCHRONOUS RAY TRACING simplified abstract
- Intel corporation (20240265487). APPARATUS AND METHOD FOR PERFORMING A STABLE AND SHORT LATENCY SORTING OPERATION simplified abstract
- Intel corporation (20240282042). APPARATUS AND METHOD FOR THROTTLING A RAY TRACING PIPELINE simplified abstract
- Intel corporation (20240282045). APPARATUS AND METHOD USING TRIANGLE PAIRS AND SHARED TRANSFORMATION CIRCUITRY TO IMPROVE RAY TRACING PERFORMANCE simplified abstract
- Intel corporation (20240320184). MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS simplified abstract
- Intel corporation (20240345990). Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page Migration simplified abstract
- Intel corporation (20240354886). UNIFIED MEMORY COMPRESSION MECHANISM simplified abstract
- Intel corporation (20240355032). GRAPHICS SYSTEM WITH ADDITIONAL CONTEXT simplified abstract
- Intel corporation (20240411717). CACHE STRUCTURE AND UTILIZATION
Categories:
- Joydeep Ray of Folsom CA (US)
- Abhishek R. Appu of El Dorado Hills CA (US)
- Altug Koker of El Dorado Hills CA (US)
- Vasanth Ranganathan of El Dorado Hills CA (US)
- Valentin Andrei of San Jose CA (US)
- Varghese George of Folsom CA (US)
- Subramaniam Maiyuran of Gold River CA (US)
- Lakshminarayanan Striramassarma of Folsom CA (US)
- Aravindh Anantaraman of Folsom CA (US)
- Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US)
- Mike Macpherson of Portland OR (US)
- Scott Janus of Loomis CA (US)
- Brent Insko of Portland OR (US)
- Nicolas Galoppo Von Borries of Portland OR (US)
- Kamal Sinha of Rancho Cordova CA (US)
- Arthur Hunter of Cameron Park CA (US)
- David Puffer of Tempe AZ (US)
- Murali Ramadoss of Folsom CA (US)
- Pattabhiraman K
- Abhishek Appu of El Dorado Hills CA (US)
- Karol Szerszen of Hillsboro OR (US)
- Eric Liskay of Folsom CA (US)
- Karthik Vaidyanathan of San Francisco CA (US)
- Lakshminarayana Striramassarma of Folsom CA (US)
- James Valerio of North Plains OR (US)
- Ankur N. Shah of Folsom CA (US)
- Ingo Wald of Salt Lake City UT (US)
- Subramaniam M. Maiyuran of Gold River CA (US)
- Balaji Vembu of Folsom CA (US)
- Guei-Yuan Lueh of San Jose CA (US)
- Sean Coleman of Folsom CA (US)
- Mike MacPherson of Portland OR (US)
- ElMoustapha Ould-Ahmed-Vall of Chandler AZ (US)
- Jayakrishna P S
- SungYe Kim of Folsom CA (US)
- Ben Ashbaugh of Folsom CA (US)
- Jonathan Pearce of Hillsboro OR (US)
- Yoav Harel of Carmichael CA (US)
- Arthur Hunter, JR. of Cameron Park CA (US)
- Marian Alin Petre of San Mateo CA (US)
- Shailesh Shah of Folsom CA (US)
- Kamal Sinha of Folsom CA (US)
- Vikranth Vemulapalli of Folsom CA (US)
- Michael J. Norris of Folsom CA (US)
- Prasoonkumar Surti of Folsom CA (US)
- Inventors
- Inventors filing patents with Intel Corporation
- Inventors filing patents with INTEL CORPORATION
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