Intel corporation (20250095693). CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER

CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER

Organization Name

intel corporation

Inventor(s)

Abhishek A. Sharma of Portland OR US

Juan G. Alzate-vinasco of Tigard OR US

Fatih Hamzaoglu of Portland OR US

Wilfred Gomes of Portland OR US

Anand S. Murthy of Portland OR US

Tahir Ghani of Portland OR US

Van H. Le of Beaverton OR US

CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER

This abstract first appeared for US patent application 20250095693 titled 'CONNECTIONS OF BIT LINES AND WORD LINES IN STACKED MEMORY LAYERS TO A COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR LAYER

Original Abstract Submitted

an ic device may include a cmos layer and memory layers at the frontside and backside of the cmos layer. the cmos layer may include one or more logic circuits, which may include mosfet transistors. a memory layer may include one or more memory arrays. a memory array may include memory cells (e.g., dram cells), bit lines, and word lines. the logic circuits may include word line drivers and sense amplifiers. word lines in different memory layers may share the same word line driver. bit lines in different memory layers may share the same sense amplifier. the ic device may include front-back word line drivers, near-far sense amplifiers, near-far word line drivers, or front-back sense amplifiers. a memory layer may be bonded with the cmos layer through a bonding layer that provides a bonding interface between the memory layer and the cmos layer.