Category:Joydeep Ray of Folsom CA (US): Difference between revisions

Joydeep Ray of Folsom CA (US)

Executive Summary

Joydeep Ray of Folsom CA (US) is an inventor who has filed 7 patents. Their primary areas of innovation include Processor architectures; Processor configuration, e.g. pipelining (5 patents), {from multiple instruction streams, e.g. multistreaming} (4 patents), {controlled by a single instruction for multiple threads [SIMT] in parallel} (4 patents), and they have worked with companies such as Intel Corporation (7 patents). Their most frequent collaborators include (6 collaborations), (6 collaborations), (4 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

• G06T1/20 (Processor architectures; Processor configuration, e.g. pipelining): 5 patents
• G06F9/3851 ({from multiple instruction streams, e.g. multistreaming}): 4 patents
• G06F9/3888 ({controlled by a single instruction for multiple threads [SIMT] in parallel}): 4 patents
• G06T1/60 (Memory management): 3 patents
• G06F9/3001 ({Arithmetic instructions}): 3 patents
• G06F9/30014 ({with variable precision}): 3 patents
• G06T15/005 ({General purpose rendering architectures}): 3 patents
• G06F9/4843 (Program initiating; Program switching, e.g. by interrupt): 2 patents
• G06F12/0866 (for peripheral storage systems, e.g. disk cache): 2 patents
• G06F12/0897 (in hierarchically structured memory systems, e.g. virtual memory systems): 2 patents
• G06F7/5443 (for evaluating functions by calculation {(): 2 patents
• G06F9/30036 ({Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}): 2 patents
• G06F9/3887 ({controlled by a single instruction for multiple data lanes [SIMD]}): 2 patents
• G06F17/16 (Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition): 2 patents
• G06N3/08 (Learning methods): 2 patents
• G06N3/044 (Recurrent networks, e.g. Hopfield networks): 2 patents
• G06N3/045 (Combinations of networks): 2 patents
• G06N3/063 (using electronic means): 2 patents
• G06F9/46 (Multiprogramming arrangements): 1 patents
• G06F9/4881 (Program initiating; Program switching, e.g. by interrupt): 1 patents
• G06F9/5027 (Allocation of resources, e.g. of the central processing unit [CPU]): 1 patents
• G06F9/522 (Program synchronisation; Mutual exclusion, e.g. by means of semaphores): 1 patents
• G06F9/545 (Interprogram communication): 1 patents
• G06F12/0842 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
• G06F15/16 (Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs {(coordinating program control therefor): 1 patents
• G06F15/76 (Architectures of general purpose stored program computers (with program plugboard): 1 patents
• G06F2209/5018 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06T2200/28 (IMAGE DATA PROCESSING OR GENERATION, IN GENERAL): 1 patents
• G06T15/503 ({Blending, e.g. for anti-aliasing}): 1 patents
• G06T11/203 ({Drawing of straight lines or curves}): 1 patents
• G06T11/40 (Filling a planar surface by adding surface attributes, e.g. colour or texture): 1 patents
• G06T15/80 (Shading): 1 patents
• G06T2200/12 (IMAGE DATA PROCESSING OR GENERATION, IN GENERAL): 1 patents
• G06F15/7839 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F7/575 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F7/588 (Random or pseudo-random number generators): 1 patents
• G06F9/3004 ({to perform operations on memory}): 1 patents
• G06F9/30043 ({LOAD or STORE instructions; Clear instruction}): 1 patents
• G06F9/30047 ({Prefetch instructions; cache control instructions}): 1 patents
• G06F9/30065 ({Loop control instructions; iterative instructions, e.g. LOOP, REPEAT}): 1 patents
• G06F9/30079 ({Pipeline control instructions, e.g. multicycle NOP}): 1 patents
• G06F9/5011 (Allocation of resources, e.g. of the central processing unit [CPU]): 1 patents
• G06F9/5077 (Allocation of resources, e.g. of the central processing unit [CPU]): 1 patents
• G06F12/0215 ({with look ahead addressing means}): 1 patents
• G06F12/0238 ({Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}): 1 patents
• G06F12/0246 ({in block erasable memory, e.g. flash memory}): 1 patents
• G06F12/0607 (Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (): 1 patents
• G06F12/0802 (Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches): 1 patents
• G06F12/0804 (with main memory updating (): 1 patents
• G06F12/0811 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
• G06F12/0862 (with prefetch): 1 patents
• G06F12/0871 (Allocation or management of cache space): 1 patents
• G06F12/0875 (with dedicated cache, e.g. instruction or stack): 1 patents
• G06F12/0882 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
• G06F12/0891 (using clearing, invalidating or resetting means): 1 patents
• G06F12/0893 (Caches characterised by their organisation or structure): 1 patents
• G06F12/0895 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
• G06F12/1009 (Address translation): 1 patents
• G06F12/128 (Replacement control): 1 patents
• G06F15/8046 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F17/18 (for evaluating statistical data {, e.g. average values, frequency distributions, probability functions, regression analysis (forecasting specially adapted for a specific administrative, business or logistic context): 1 patents
• H03M7/46 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
• G06F9/3802 ({Instruction prefetching}): 1 patents
• G06F9/3818 ({Decoding for concurrent execution}): 1 patents
• G06F9/3867 ({using instruction pipelines}): 1 patents
• G06F2212/1021 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2212/1044 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2212/302 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2212/401 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2212/455 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2212/60 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06T15/06 (Ray-tracing): 1 patents
• G06F3/14 (Digital output to display device {; Cooperation and interconnection of the display device with other functional units}): 1 patents
• G06F9/3017 ({Runtime instruction translation, e.g. macros}): 1 patents
• G06F9/3895 ({for complex operations, e.g. multidimensional or interleaved address generators, macros}): 1 patents
• G06N3/084 (Backpropagation, e.g. using gradient descent): 1 patents
• G09G5/363 (ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays): 1 patents
• G06T15/04 (Texture mapping): 1 patents
• G09G2360/06 (ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays): 1 patents
• G09G2360/08 (ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays): 1 patents
• G09G2360/121 (ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays): 1 patents
• G06F7/483 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G09G5/393 (ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays): 1 patents
• G06F1/16 (Constructional details or arrangements): 1 patents
• G06F9/30025 ({Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion}): 1 patents
• G06F9/3013 ({according to data content, e.g. floating-point registers, address registers}): 1 patents
• G06F2207/3824 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06N20/00 (Machine learning): 1 patents
• G06F9/3009 ({Thread control instructions}): 1 patents
• G06F9/30185 ({according to one or more bits in the instruction, e.g. prefix, sub-opcode}): 1 patents
• G06F9/461 (Multiprogramming arrangements): 1 patents
• G06T2200/04 (IMAGE DATA PROCESSING OR GENERATION, IN GENERAL): 1 patents

Companies

List of Companies

• Intel Corporation: 7 patents

Collaborators

• Abhishek R. Appu of El Dorado Hills CA (US) (6 collaborations)
• Altug Koker of El Dorado Hills CA (US) (6 collaborations)
• Balaji Vembu of Folsom CA (US) (4 collaborations)
• Prasoonkumar Surti of Folsom CA (US) (3 collaborations)
• Vasanth Ranganathan of El Dorado Hills CA (US) (2 collaborations)
• Kamal Sinha of Rancho Cordova CA (US) (2 collaborations)
• David Puffer of Tempe AZ (US) (2 collaborations)
• Ping T. Tang of Edison NJ (US) (2 collaborations)
• Michael S. Strickland of Sunnyvale CA (US) (2 collaborations)
• Xiaoming Chen (2 collaborations)
• Anbang Yao (2 collaborations)
• Tatiana Shpeisman of Menlo Park CA (US) (2 collaborations)
• Aravindh Anantaraman of Folsom CA (US) (1 collaborations)
• Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) (1 collaborations)
• Valentin Andrei of San Jose CA (US) (1 collaborations)
• Nicolas Galoppo Von Borries of Portland OR (US) (1 collaborations)
• Varghese George of Folsom CA (US) (1 collaborations)
• Mike Macpherson of Portland OR (US) (1 collaborations)
• Subramaniam Maiyuran of Gold River CA (US) (1 collaborations)
• Lakshminarayana Striramassarma of Folsom CA (US) (1 collaborations)
• Scott Janus of Loomis CA (US) (1 collaborations)
• Brent Insko of Portland OR (US) (1 collaborations)
• Arthur Hunter of Cameron Park CA (US) (1 collaborations)
• James Valerio of North Plains OR (US) (1 collaborations)
• Ankur N. Shah of Folsom CA (US) (1 collaborations)
• Linda L. Hurd of Cool CA (US) (1 collaborations)
• Dukhwan Kim of San Jose CA (US) (1 collaborations)
• Mike B. Macpherson of Portland OR (US) (1 collaborations)
• John C. Weast of Portland OR (US) (1 collaborations)
• Feng Chen (1 collaborations)
• Farshad Akhbari of Chandler AZ (US) (1 collaborations)
• Narayan Srinivasa of Portland OR (US) (1 collaborations)
• Nadathur Rajagopalan Satish of Santa Clara CA (US) (1 collaborations)
• Himanshu Kaul of Portland OR (US) (1 collaborations)
• Mark A. Anders of Hillsboro OR (US) (1 collaborations)
• Sanu K. Mathew of Hillsboro OR (US) (1 collaborations)
• Nicolas C. Galoppo Von Borries of Portland OR (US) (1 collaborations)
• Eriko Nurvitadhi of Hillsboro OR (US) (1 collaborations)
• Rajkishore Barik of Santa Clara CA (US) (1 collaborations)
• Tsung-Han Lin of Campbell CA (US) (1 collaborations)
• Sanjeev Jahagirdar of Folsom CA (US) (1 collaborations)
• Ingo Wald of Salt Lake City UT (US) (1 collaborations)
• Subramaniam M. Maiyuran of Gold River CA (US) (1 collaborations)
• Guei-Yuan Lueh of San Jose CA (US) (1 collaborations)
• Murali Ramadoss of Folsom CA (US) (1 collaborations)