Micron technology, inc. (20250086055). REDUNDANT ARRAY MANAGEMENT TECHNIQUES
REDUNDANT ARRAY MANAGEMENT TECHNIQUES
Organization Name
Inventor(s)
Chun Sum Yeung of San Jose CA (US)
Jonathan S. Parry of Boise ID (US)
Xiangang Luo of Fremont CA (US)
REDUNDANT ARRAY MANAGEMENT TECHNIQUES
This abstract first appeared for US patent application 20250086055 titled 'REDUNDANT ARRAY MANAGEMENT TECHNIQUES
Original Abstract Submitted
methods, systems, and devices for redundant array management techniques are described. a memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. the memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. the memory system may receive a write command associated with writing data to a type of memory cell. based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. in some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.
