Category:Xiang Yang of Santa Clara CA (US)
Xiang Yang of Santa Clara CA (US)
Executive Summary
Xiang Yang of Santa Clara CA (US) is an inventor who has filed 9 patents. Their primary areas of innovation include {comprising cells having several storage transistors connected in series} (4 patents), Address circuits; Decoders; Word-line control circuits (4 patents), Programming or data input circuits (3 patents), and they have worked with companies such as Western Digital Technologies, Inc. (9 patents). Their most frequent collaborators include (4 collaborations), (3 collaborations), (1 collaborations).
Patent Filing Activity
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Technology Areas
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List of Technology Areas
- G11C16/0483 ({comprising cells having several storage transistors connected in series}): 4 patents
- G11C16/08 (Address circuits; Decoders; Word-line control circuits): 4 patents
- G11C16/10 (Programming or data input circuits): 3 patents
- G11C16/16 (STATIC STORES (semiconductor memory devices): 2 patents
- G11C16/26 (Sensing or reading circuits; Data output circuits): 2 patents
- G11C29/46 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C29/18 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C2029/1202 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C11/4074 (Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits): 1 patents
- G11C16/24 (Bit-line control circuits): 1 patents
- G11C29/022 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C29/1201 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C29/36 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C2029/3602 (STATIC STORES (semiconductor memory devices): 1 patents
- G06F3/0613 ({in relation to throughput}): 1 patents
- G06F3/0634 ({by changing the state or mode of one or more devices}): 1 patents
- G06F3/064 ({Management of blocks}): 1 patents
- G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 1 patents
- G06F13/1694 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G11C16/3445 ({Circuits or methods to verify correct erasure of nonvolatile memory cells}): 1 patents
- H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2225/06562 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- G11C16/3459 ({Circuits or methods to verify correct programming of nonvolatile memory cells}): 1 patents
- G11C16/0433 ({comprising cells containing a single floating gate transistor and one or more separate select transistors}): 1 patents
Companies
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List of Companies
- Western Digital Technologies, Inc.: 9 patents
Collaborators
- Abhijith Prakash of Milpitas CA (US) (4 collaborations)
- Wei Cao of Fremont CA (US) (3 collaborations)
- Jiahui Yuan of Fremont CA (US) (1 collaborations)
- Mohan Vamsi Dunga of Santa Clara CA (US) (1 collaborations)
- Parth Amin of Livermore CA (US) (1 collaborations)
- Dengtao Zhao of Los Gatos CA (US) (1 collaborations)
- Peng Zhang of San Jose CA (US) (1 collaborations)
- Jiacen Guo of Cupertino CA (US) (1 collaborations)
- Henry Chin of San Jose CA (US) (1 collaborations)
Subcategories
This category has the following 3 subcategories, out of 3 total.
A
J
X
Pages in category "Xiang Yang of Santa Clara CA (US)"
The following 12 pages are in this category, out of 12 total.
1
- 18223358. GENERATION OF QUICK PASS WRITE BIASES IN A MEMORY DEVICE simplified abstract (WESTERN DIGITAL TECHNOLOGIES, INC.)
- 18225735. LOOP DEPENDENT BIT LINE AND READ BIASES IN A MEMORY DEVICE simplified abstract (WESTERN DIGITAL TECHNOLOGIES, INC.)
- 18229705. READ POWER SAVINGS BY TEMPORARILY DISABLING BITLINE VOLTAGE (Western Digital Technologies, Inc.)
- 18230270. OPEN BLOCK DETECTION METHOD USING FOR FIRST AND SECOND TIME PERIOD READ TIME VALLEY FOR NON-VOLATILE MEMORY APPARATUS (Western Digital Technologies, Inc.)
- 18230371. CHANNEL PRE-CHARGE PROCESS FOR MEMORY DEVICES (Western Digital Technologies, Inc.)
U
- US Patent Application 17825048. HIGH SPEED MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES simplified abstract
- US Patent Application 17825193. LOW POWER MULTI-LEVEL CELL (MLC) PROGRAMMING IN NON-VOLATILE MEMORY STRUCTURES simplified abstract
- US Patent Application 17828685. NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT simplified abstract
W
- Western digital technologies, inc. (20240420773). READ POWER SAVINGS BY TEMPORARILY DISABLING BITLINE VOLTAGE
- Western digital technologies, inc. (20240420775). OPEN BLOCK DETECTION METHOD USING FOR FIRST AND SECOND TIME PERIOD READ TIME VALLEY FOR NON-VOLATILE MEMORY APPARATUS
- Western digital technologies, inc. (20240420779). CHANNEL PRE-CHARGE PROCESS FOR MEMORY DEVICES
- Western digital technologies, inc. (20240427662). SINGLE BLOCK MODE BLOCK HANDLING FOR SINGLE-SIDE GIDL ERASE
Categories:
- Abhijith Prakash of Milpitas CA (US)
- Wei Cao of Fremont CA (US)
- Jiahui Yuan of Fremont CA (US)
- Mohan Vamsi Dunga of Santa Clara CA (US)
- Parth Amin of Livermore CA (US)
- Dengtao Zhao of Los Gatos CA (US)
- Peng Zhang of San Jose CA (US)
- Jiacen Guo of Cupertino CA (US)
- Henry Chin of San Jose CA (US)
- Xiang Yang of Santa Clara CA (US)
- Inventors
- Inventors filing patents with Western Digital Technologies, Inc.