Category:Akira Goda of Tokyo JP
Akira Goda
Akira Goda from Tokyo JP has applied for patents in technology areas such as G06F3/06 with micron technology, inc..
Patents
Pages in category "Akira Goda of Tokyo JP"
The following 12 pages are in this category, out of 12 total.
1
- 18768974. SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING BY CREATING A PSEUDO PN JUNCTION (Micron Technology, Inc.)
- 18901899. CALIBRATING DATA RELOCATION FROM BUFFER TO MEMORY DEVICE IN A MEMORY SUB-SYSTEM (MICRON TECHNOLOGY, INC.)
- 19008498. PARALLELIZED DEFECT DETECTION ACROSS MULTIPLE SUB-BLOCKS IN A MEMORY DEVICE (Micron Technology, Inc.)
2
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- Micron technology, inc. (20250013382). QUICK CHARGE LOSS MITIGATION USING TWO-PASS CONTROLLED DELAY
- Micron technology, inc. (20250014655). READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS
- Micron technology, inc. (20250130736). CALIBRATING DATA RELOCATION FROM BUFFER TO MEMORY DEVICE IN A MEMORY SUB-SYSTEM
- Micron technology, inc. (20250140317). PARALLELIZED DEFECT DETECTION ACROSS MULTIPLE SUB-BLOCKS IN A MEMORY DEVICE
- Micron technology, inc. (20250140322). SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING BY CREATING A PSEUDO PN JUNCTION