TEXAS INSTRUMENTS INCORPORATED patent applications published on November 30th, 2023

Patent applications for TEXAS INSTRUMENTS INCORPORATED on November 30th, 2023

QUICK TURN OFF OF CONTACTOR SYSTEM DURING POWER OFF (17826822)

Main Inventor

Priyank Anand

Brief explanation

The patent application describes a system for quickly turning off a contactor controller when the supply voltage is below a certain threshold. This system ensures that the quick-turn-off (QTO) function is not affected when there is sufficient supply voltage available.

• The contactor controller disables the high-side (HS) clamp when there is a loss of supply voltage (VM loss).
• The output voltage is used to generate a low-side (LS) clamp current, which can be adjusted to achieve the desired QTO voltage.
• In another example, the HS clamp is disabled and the gate of a LS field-effect transistor (FET) is charged only when the output voltage increases above a power-off QTO threshold.
• The QTO voltage is determined by a voltage detection and comparison circuit of the contactor controller.

Abstract

Examples of contactor controllers, systems and methods enable quick-turn-off (QTO) using an output voltage of a contactor controller when its supply voltage is below a threshold but does not interfere with QTO when sufficient supply voltage is available. In an example, when VM loss occurs, a high-side (HS) clamp of a contactor controller is disabled, and a low-side (LS) clamp current is generated using the output voltage. The LS clamp current may be adjusted to achieve a desired QTO voltage. In another example, a HS clamp is disabled and the charging of the gate of a LS field-effect transistor (FET) is enabled only when the output voltage increases above a power-off QTO threshold (less than the LS clamp voltage); the QTO voltage is set by a voltage detection and comparison circuit of the contactor controller.

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS (18234003)

Main Inventor

Lee D. Whetsel

Brief explanation

- The patent application describes a test architecture for integrated circuits.

- The architecture includes a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface. - The test interface consists of a scan input, a scan clock, a test enable, and a scan output. - Scan frames are used to input test stimulus data and test commands into the shift register. - The output shift register produces scan frames with test response data and potentially other output data. - The command section of the input scan frame controls the test architecture to perform the desired test operation.

• The patent application aims to improve the testing process for integrated circuits.
• It introduces a test architecture that utilizes shift registers and a test interface.
• The architecture allows for the input of test stimulus data and commands.
• It also enables the output of test response data and potentially other output data.
• The command section of the input scan frame controls the execution of desired test operations.

Abstract

Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

FSM BASED CLOCK SWITCHING OF ASYNCHRONOUS CLOCKS (17824695)

Main Inventor

Atul Ramakant LELE

Brief explanation

The patent application describes an apparatus that includes a clock switching circuit coupled to oscillators and circuit units.

• The clock switching circuit receives frequency signals from the oscillators and provides an uplink primary clock signal and an enable signal to the circuit units.
• The enable signal is determined synchronously with the uplink primary clock signal.
• The clock switching circuit also receives a clock frequency request from the circuit units or a clock management circuit.
• Based on the request, the clock switching circuit provides the uplink primary clock signal using either the first signal or the second signal from the set of frequency signals.

Abstract

Aspects of the disclosure provide for an apparatus. In an example, the apparatus includes a clock switching circuit coupled to oscillators and one or more circuit units. The clock switching circuit is configured to receive, from the oscillators, a set of frequency signals, provide an uplink primary clock signal and an enable signal to the one or more circuit units, the enable signal determined synchronously with the uplink primary clock signal, receive, from the one or more circuit units or a clock management circuit, a clock frequency request, provide the uplink primary clock signal based on a first signal of the set of frequency signals, and according to the clock frequency request, determining whether to continue to provide the uplink primary clock signal based on the first signal or on a second signal of the set of frequency signals.

STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS (18450079)

Main Inventor

Oluleye Olorode

Brief explanation

The patent application describes a dNap architecture that efficiently manages cache lines to reduce power consumption without affecting performance.

• The dNap architecture accurately transitions cache lines to a full power state before they are accessed, eliminating delays caused by waking up drowsy lines.
• Only cache lines that are predicted to be accessed in the immediate future are fully powered, while others are put in a drowsy mode to save power.
• This approach significantly reduces leakage power without impacting cache performance.
• The hardware overhead required for implementing this architecture is minimal, especially for caches with higher associativities.
• The dNap architecture achieves up to 92% static/leakage power savings with minimal hardware overhead and no performance tradeoff.

Abstract

Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

CONFIGURABLE CACHE FOR COHERENT SYSTEM (18229814)

Main Inventor

Kai CHIRCA

Brief explanation

The patent application describes a device with a memory bank that has data portions organized into two groups called "first way group" and "second way group".

• The first way group includes data portions from two different ways.
• The memory bank also includes data portions from the second way group.

The device includes a configuration register and a controller that can allocate the first way and the second way to either an addressable memory space or a data cache.

• The allocation is based on settings in the configuration register.
• The controller can allocate the first way and the second way individually, meaning they can be assigned to different memory spaces or caches.
• This allocation process allows for efficient management of memory resources based on the specific needs of the device.

Abstract

A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

STREAMING ENGINE WITH EARLY EXIT FROM LOOP LEVELS SUPPORTING EARLY EXIT LOOPS AND IRREGULAR LOOPS (18361985)

Main Inventor

Joseph Zbiciak

Brief explanation

The abstract describes a streaming engine used in a digital data processor that generates a fixed read-only data stream with nested loops.

• The streaming engine uses an address generator to produce addresses of data elements.
• A stream head register stores the data elements that will be used as operands by functional units.
• When a stream break instruction is encountered, the streaming engine ends the current iteration of the loop.
• If the specified loop is not the outermost loop, the streaming engine starts an iteration of the next outer loop.
• If the specified loop is the outermost nested loop, the streaming engine ends the stream.
• The streaming engine organizes a vector of data elements in order within lanes of the stream head register.
• A stream break instruction can also be used to break the vector.

Abstract

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Upon a stream break instruction specifying one of the nested loops, the stream engine ends a current iteration of the loop. If the specified loop was not the outermost loop, the streaming engine begins an iteration of a next outer loop. If the specified loop was the outermost nested loop, the streaming engine ends the stream. The streaming engine places a vector of data elements in order in lanes within a stream head register. A stream break instruction is operable upon a vector break.

HARDWARE EVENT TRIGGERED PIPELINE CONTROL (18175364)

Main Inventor

Niraj Nandan

Brief explanation

- The patent application is about hardware enabled pipeline control in a hardware acceleration system.

- The system includes pipelines with a hardware enable flag that allows hardware initiation of the pipeline based on a configurable event. - The pipeline can be configured to set the event that triggers the initiation of the pipeline. - This means that a second pipeline can be initiated automatically when the first pipeline reaches its end. - By allowing hardware enable based on a specifically configured event, the system avoids the extra processing required to initiate the pipeline via software in external memory and triggered by an external controller.

Abstract

Various embodiments disclosed herein relate to hardware enabled pipeline control. In a hardware acceleration system, pipelines are configured to include a hardware enable flag that allows hardware initiation of the pipeline based on triggering of a configurable event. The pipeline can be configured to set the event that triggers the initiation of the pipeline. For example, the end of pipeline of a first pipeline may trigger the initiation of a second pipeline. Accordingly, pipelines that are configured to allow hardware enable based on a specifically configured event are not subject to the extra processing required to initiate the pipeline via software in external memory and triggered by an external controller.

RESOURCE AVAILABILITY MANAGEMENT USING REAL-TIME TASK MANAGER IN MULTI-CORE SYSTEM (18449036)

Main Inventor

Anjandeep Singh SAHNI

Brief explanation

The patent application describes a method for allocating computing resources.

• The method involves performing a first task and determining that a specific operation requires an external resource.
• If the resource is unavailable, the first task is paused and a second task is started.
• Once the resource becomes available, the first task is resumed from where it left off.

This method aims to efficiently allocate computing resources by pausing tasks when necessary and resuming them when the required resources are available.

Abstract

A computing resource allocation method comprises beginning a first performance of a first task; determining, using a task manager circuit during the first performance of the first task, that a first operation from among the first plurality of operations requires a resource, wherein the resource is external to the processor; determining, using a spinlock circuit, that the resource is unavailable for use; pausing, under control of the task manager, the first performance of the first task at the processor; beginning, using the processor, a second performance of a second task, the second task comprising a second plurality of operations; receiving, at the task manager, a notice from the spinlock that the resource is currently available for use by the processor; and resuming, under control of the task manager, the first performance of the first task at the processor starting with the first operation from among the first plurality of operations.

DATA PROCESSING PIPELINE (18175333)

Main Inventor

Mihir Mody

Brief explanation

The patent application describes a data processing device that includes multiple hardware accelerators, a scheduler circuit, and a blocking circuit.

• The data processing device has hardware accelerators, which are specialized circuits designed to perform specific tasks quickly.
• The scheduler circuit is connected to the hardware accelerators and consists of multiple hardware task schedulers.
• Each hardware task scheduler is linked to a specific hardware accelerator and controls the execution of tasks by that accelerator.
• The blocking circuit is also connected to the hardware accelerators and is designed to prevent communication between two specific hardware accelerators.
• The purpose of the blocking circuit is to restrict the interaction between certain hardware accelerators, possibly to avoid conflicts or optimize performance.

Abstract

A data processing device includes a plurality of hardware accelerators, a scheduler circuit, and a blocking circuit. The scheduler circuit is coupled to the plurality of hardware accelerators, and includes a plurality of hardware task schedulers. Each hardware task scheduler is coupled to a corresponding hardware accelerator, and is configured to control execution of the task by the hardware accelerator. The blocking circuit is coupled to the plurality of hardware accelerators and configured to inhibit communication between a first hardware accelerator and a second hardware accelerator of the plurality of hardware task schedulers.

FFT ENGINE HAVING COMBINED BIT-REVERSAL AND MEMORY TRANSPOSE OPERATIONS (18447029)

Main Inventor

Indu PRATHAPAN

Brief explanation

The patent application describes a data processing device that performs Fast Fourier Transform (FFT) on digital input signals and stores the output samples in memory.

• The device includes FFT logic that generates FFT output samples for each digital input signal.
• It has a first memory device with multiple banks and a second memory device.
• A bit-reversed address generator and a first set of circular shift components are used to write the FFT output samples in bit-reversed address order to the first memory device, allowing efficient storage.
• A second set of circular shift components is used to read the FFT output samples from the first memory device in linear address order and store them in the second memory device.
• The first and second set of circular shift components work together to read the FFT output samples in transpose order, combining bit-reversal and memory transpose operations for improved efficiency.

Abstract

A data processing device includes: 1) Fast Fourier Transform (FFT) logic configured to generate FFT output samples for each of a plurality of digital input signals; 3) a first memory device with a plurality of banks; 4) a second memory device; 5) a bit-reversed address generator and first set of circular shift components configured to shift between the plurality of banks when writing the generated FFT output samples in bit-reversed address order to the first memory device; and 6) a second set of circular shift components configured to shift between the plurality of banks when reading FFT output samples in linear address order from the first memory device for storage in the second memory device, wherein the first and second set of circular shift components together are configured to read FFT output samples in transpose order using combined bit-reversal and memory transpose operations.

THEFT DETECTOR (18326176)

Main Inventor

Veeramanikandan RAJU

Brief explanation

- The patent application describes an end-user computing device with a theft detector.

- The theft detector maintains a list of registered host devices. - The theft detector has root access to the operations of the end-user device. - If a possible theft condition is detected, the theft detector provides a secure reboot request. - The end-user device includes a boot loader that executes a secure reboot in response to the request. - The secure reboot resets the end-user device to prevent unauthorized access.

Abstract

An end-user computing device can include a theft detector that maintains a registered host device list containing identifiers of at least one registered host device. The theft detector can have root access to operations of the end-user device and the theft detector can provides a secure reboot request in response to detecting a possible theft condition. The end-user computing device can also include a boot loader that executes a secure reboot of the end-user device in response to a secure reboot request from the theft detector. The secure reboot of the end-user device resets the end-user device to prevent access to the end-user device.

TRANSFORMER WITH BOTTOM COIL SHIELDING FOR IMPROVED EMI AND THERMAL CHARACTERISTICS (17829073)

Main Inventor

Nicola BERTONI

Brief explanation

The patent application describes an apparatus that includes multiple conductive layers on a substrate.

• The first conductive layer acts as an electromagnetic interference (EMI) shield.
• The second conductive layer includes the first winding of a transformer.
• The third conductive layer acts as another EMI shield.
• The fourth conductive layer includes the second winding of the transformer.

Abstract

An apparatus includes a substrate and first through fourth conductive layers. The first conductive layer is on the substrate and includes a first electromagnetic interference (EMI) shield. The second conductive layer is over the first conductive layer opposite the substrate and includes a first winding of a transformer. The third conductive layer is over the second conductive layer opposite the first conductive layer and includes a second EMI shield. The fourth conductive layer is over the third conductive layer opposite the second conductive layer and includes a second winding of the transformer.

DIELECTRIC SILICON NITRIDE BARRIER DEPOSITION PROCESS FOR IMPROVED METAL LEAKAGE AND ADHESION (17751976)

Main Inventor

Qi-Zhong Hong

Brief explanation

- The patent application describes an electronic device that includes a semiconductor die with a multilevel metallization structure.

- The multilevel metallization structure consists of stacked levels with dielectric layers and metal lines. - One of the stacked levels has a low leakage, low hydrogen diffusion barrier layer. - The diffusion barrier layer is in contact with a side of the dielectric layer and the metal line of that particular stacked level. - The diffusion barrier layer is made of silicon nitride material. - The silicon nitride material has a higher percentage ratio of ammonia to silicon nitride compared to the percentage ratio of silicon hydride to silicon nitride. - The higher ammonia percentage ratio in the diffusion barrier layer helps to reduce leakage and hydrogen diffusion in the electronic device.

Abstract

An electronic device includes a semiconductor die having a multilevel metallization structure including stacked levels with respective dielectric layers and metal lines, and a low leakage, low hydrogen diffusion barrier layer on one of the stacked levels. The diffusion barrier layer contacts a side of the dielectric layer and the metal line of the one of the stacked levels, and the diffusion barrier layer includes silicon nitride material having a first bond percentage ratio of ammonia to silicon nitride that is greater than a second bond percentage ratio of silicon hydride to silicon nitride.

REDUCING CROSS-WAFER VARIABILITY FOR MINIMUM WIDTH RESISTORS (18446176)

Main Inventor

Mahalingam Nandakumar

Brief explanation

- This patent application is about a method for fabricating an integrated circuit.

- The method involves applying a photoresist layer on a substrate. - The substrate has target regions that need to be exposed. - A reticle is used to define a first exposure window for a first doped structure of a first type. - The first exposure window has multiple openings and dopant blocking regions. - An exposure map is used to determine the exposure dose for each target region. - The exposure dose controls the size variations of the openings across the target regions. - After exposure and developing the photoresist, a dopant is implanted into the substrate through the openings. - The innovation lies in the controlled variations in the size of the openings, which can improve the performance and functionality of the integrated circuit.

Abstract

Fabrication of an integrated circuit includes forming a photoresist layer over a substrate. Target regions defined on the substrate are exposed using a reticle that defines a first exposure window for a first doped structure of a first type; the first exposure window has a first plurality of openings and a first plurality of dopant blocking regions. A respective exposure dose for each of the target regions is determined by an exposure map and provides controlled variations in the size of the first plurality of openings across the plurality of target regions. Subsequent to the exposure and to developing the photoresist, a dopant is implanted into the substrate through the first plurality of openings.

POWER CONVERTER MODULE (17828803)

Main Inventor

WOOCHAN KIM

Brief explanation

The patent application describes a power converter module that includes a substrate with two opposing surfaces.

• The module includes a thick printed copper (TPC) substrate on the first surface of the substrate.
• The TPC substrate consists of three layers: the first layer has TPC patterned on the first surface of the substrate, the second layer has dielectric patterned on the first layer, and the third layer has TPC patterned on the second layer.
• Power transistors are mounted on the TPC substrate, and a control integrated circuit (IC) chip is also mounted on the TPC substrate.

Abstract

A power converter module includes a substrate having a first surface and a second surface that opposes the first surface. The power converter module includes a thick printed copper (TPC) substrate on the first surface of the substrate. The TPC substrate includes a first layer having TPC patterned on the first surface of the substrate and a second layer with dielectric patterned on the first layer. The TPC substrate includes a third layer having TPC patterned on the second layer. The power converter module includes power transistors mounted on the TPC substrate and a control integrated circuit (IC) chip mounted on the TPC substrate.

DIE ATTACH FILM DIE PAD ISOLATION FOR SEMICONDUCTOR DEVICES (17828947)

Main Inventor

Jesus Bajo Bautista

Brief explanation

The patent application describes an apparatus for packaging a semiconductor device.

• The apparatus includes a semiconductor die mounted on a lead frame using a die attach film.
• Bond pads on the semiconductor die are connected to leads of the lead frame using bond wires.
• The semiconductor die, bond wires, and portions of the lead frame are covered with a mold compound.
• Some portions of the leads are exposed from the mold compound to form terminals of the packaged semiconductor device.
• The die attach film has a partially cut layer with a cut side edge and an uncut layer with a torn side edge.

Abstract

In a described example, an apparatus includes: a semiconductor die having a device side surface and an opposing backside surface, the backside surface mounted to a die pad of a lead frame using a die attach film; bond pads overlying the device side surface of the semiconductor die; bond wires electrically coupling the bond pads to leads of the lead frame spaced from the die pad; and mold compound covering the semiconductor die, the bond wires, and portions of the lead frame, where portions of the leads are exposed from the mold compound to form terminals of the packaged semiconductor device. The die attach film has a partially cut die attach film layer with a cut side edge normal to the backside surface, and the die attach film has an uncut die attach film layer with a torn side edge normal to the backside surface.

LASER ABLATION FOR DIE SEPARATION TO REDUCE LASER SPLASH AND ELECTRONIC DEVICE (17826764)

Main Inventor

Michael Todd Wyant

Brief explanation

- The patent application describes a method for removing a portion of a wafer to create a trench between adjacent die regions.

- The trench is formed by using a laser ablation process that goes through the metallization structure and active circuit portion of the wafer. - The bottom of the trench is not connected to the second side of the wafer. - After the laser ablation process, a wafer expansion process is performed to separate individual semiconductor dies from the wafer.

Abstract

A method includes performing a laser ablation process that removes a portion of a wafer to form a trench in a scribe region between adjacent die regions of the wafer, the trench extending from a first side of the wafer toward an opposite second side of the wafer, the trench extending through a metallization structure and an active circuit portion of the wafer, and a bottom of the trench spaced apart from the second side of the wafer. The method also includes performing a wafer expansion process that separates individual semiconductor dies from the wafer after the laser ablation process.

INTEGRATED MAGNETIC ASSEMBLY WITH CONDUCTIVE FIELD PLATES (18450291)

Main Inventor

Enis Tuncer

Brief explanation

The abstract describes an electronic device that includes a magnetic assembly with a multilevel lamination or metallization structure. This structure consists of a core layer, dielectric layers, and conductive features formed in metal layers.

• The device has a multilevel lamination or metallization structure.
• The structure includes a core layer, dielectric layers, and conductive features.
• The conductive features are formed in metal layers on or between the dielectric layers.
• The conductive features are arranged in orthogonal first and second directions and stacked along an orthogonal third direction.
• The conductive features include windings, capacitor plates, and field plates.
• The windings are formed by first and second patterned conductive features.
• The capacitor plates are formed by first and second conductive features.
• The field plates are also formed by first and second conductive features.
• The first conductive capacitor plate is positioned between the first conductive field plate and the core layer along the third direction.
• The second conductive capacitor plate is positioned between the second conductive field plate and the core layer along the third direction.

Abstract

An electronic device includes a magnetic assembly with a multilevel lamination or metallization structure having a core layer, dielectric layers and conductive features formed in metal layers on or between the dielectric layers in respective planes of orthogonal first and second directions and stacked along an orthogonal third direction. The conductive features include first and second patterned conductive features forming first and second windings, first and second conductive capacitor plates, and first and second conductive field plates, in which the first conductive capacitor plate is between the first conductive field plate and the core layer along the third direction and the second conductive capacitor plate is between the second conductive field plate and the core layer along the third direction.

SELECTIVE EPITAXY TO CREATE A DOUBLE-DIFFUSED CHANNEL OVER PLANAR OR UNDERLYING TOPOGRAPHY (17826872)

Main Inventor

Sheldon Douglas HAYNIE

Brief explanation

The patent application describes a method for forming a gate on a semiconductor layer of a substrate. Here are the key points:

• A gate is formed on a semiconductor layer of a substrate.
• A hard mask is formed over the gate and the semiconductor layer, exposing a portion of the semiconductor layer.
• The exposed portion of the semiconductor layer is etched away in a specific manner to create a recess with a certain depth.
• A first selective epitaxial growth is performed, where a first semiconductor material doped with a first dopant is grown on the semiconductor layer within the recess.
• A second selective epitaxial growth is performed, where a second semiconductor material doped with a second dopant is grown on top of the first semiconductor material within the recess.
• Finally, the hard mask is removed.

Abstract

A method includes forming a gate on a semiconductor layer of a substrate. A hard mask is formed over the gate and the semiconductor layer to expose a portion of the semiconductor layer. The exposed portion of the semiconductor layer is isotropically etched away to form a recess having a depth. A first selective epitaxial growth of a first semiconductor material doped with a first dopant is performed on the semiconductor layer in the recess. A second selective epitaxial growth of a second semiconductor material doped with a second dopant is performed on the first semiconductor material in the recess. The hard mask is then removed.

SYSTEM AND METHOD FOR ESTIMATING A CURRENT IN AN INDUCTOR OF A POWER CONVERTER (17829090)

Main Inventor

Isaac Cohen

Brief explanation

The patent application describes a current estimating circuit that is used in electronic devices.

• The circuit includes a resistor and a capacitor that work together to measure the current flowing through an inductor.
• During the first part of a switching cycle, the voltage across the capacitor is proportional to the inductor current.
• The circuit also includes a sense resistor that provides a sensed voltage during the second part of the switching cycle.
• A switch is used to apply the sensed voltage to the capacitor, allowing it to provide the voltage measurement during the second part of the cycle.

Abstract

In an example, a current estimating circuit includes a current estimating resistor coupled in series with a current estimating capacitor. The current estimating resistor and the current estimating capacitor are configured to provide a voltage across the current estimating capacitor during a first portion of a switching cycle, in which the voltage across the current estimating capacitor is proportional to an inductor current that flows through an inductor. The current estimating circuit includes a sense resistor configured to provide a sensed voltage across the sense resistor during a second portion of the switching cycle. The current estimating circuit includes a switch configured to apply the sensed voltage to the current estimating capacitor to provide the voltage across the current estimating capacitor during the second portion of the switching cycle.

ADAPTIVE ON-TIME FOR VOLTAGE CONVERTER (17829035)

Main Inventor

Sombuddha CHAKRABORTY

Brief explanation

The patent application describes a voltage converter that includes a switch network, a rectifier, and a transformer.

• The voltage converter has an adaptive ON-time generation circuit that controls the switch network.
• The adaptive ON-time generation circuit receives a WAKE signal to turn ON the switch network.
• It generates a signal that represents the OFF time of the switch network.
• Based on this signal, the adaptive ON-time generation circuit determines the ON time for the switch network.
• The purpose of this innovation is to improve the efficiency and performance of the voltage converter.

Abstract

A voltage converter includes a switch network, a rectifier, and a transformer coupled between the switch network and the rectifier. The voltage converter includes an adaptive ON-time generation circuit having a control input and a control output, the control input. The adaptive ON-time generation circuit is configured to receive a WAKE signal to turn ON the switch network, generate a signal indicative of an OFF time of the switch network, and determine an ON time for the switch network based on the signal indicative of the OFF time.

PRE-BIASED DUAL CURRENT SENSING (17827406)

Main Inventor

Venkatesh GUDURI

Brief explanation

The patent application describes a system that includes transistors and circuitry to provide current to a load. It also includes a sense transistor to measure the current flowing through one of the transistors. An amplifier is connected to the sense transistor and has inputs and an output. Pre-bias circuitry is included to provide a voltage to the amplifier when the first transistor is off, which helps to bias the amplifier.

• The system includes transistors and circuitry to provide current to a load.
• A sense transistor is used to measure the current flowing through one of the transistors.
• An amplifier is connected to the sense transistor and has inputs and an output.
• Pre-bias circuitry is included to provide a voltage to the amplifier when the first transistor is off.
• The voltage from the pre-bias circuitry helps to bias the amplifier.

Abstract

In an example, a system includes a first transistor and a second transistor, the first transistor and the second transistor configured to provide current to a load. The system also includes a sense transistor coupled to the first transistor, the sense transistor configured to sense a current flowing through the first transistor. The system includes an amplifier coupled to the sense transistor, where the amplifier includes a first input, a second input, and an output. The system also includes pre-bias circuitry coupled to the amplifier, where the pre-bias circuitry is configured to provide a voltage to the first input of the amplifier responsive to the first transistor being off, where the voltage biases the amplifier.

FLOATING HIGH-VOLTAGE LEVEL TRANSLATOR WITH ADAPTIVE BYPASS CIRCUIT (17828797)

Main Inventor

Tuli Luthuli Dake

Brief explanation

- The patent application describes techniques to improve floating level translators.

- These translators are used to convert signals from a low-voltage domain to a high-voltage domain. - The techniques involve bypassing the protection elements of the translator to increase headroom. - A bypass circuit is added across the protection elements. - The bypass circuit is activated during low-voltage operation to provide a lower loss path. - The bypass circuit disengages when the high-voltage reference rail exceeds a threshold. - The bypass circuit can be implemented using back-to-back high-voltage FETs. - No additional signals are needed to control the low-voltage capability of the translator.

Abstract

Techniques are described herein to enhance capability of floating level translators. For example, increased headroom is accomplished by adaptively bypassing the protection elements of the voltage level translator. In an example, a floating level translator can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit is coupled across the protection elements. The bypass circuit selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low-voltage domain power rail). The bypass circuit can be implemented in a relatively low-complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.

ADJUSTABLE PHASE LOCKED LOOP (18448319)

Main Inventor

Florian Neveu

Brief explanation

The patent application describes a phase locked loop (PLL) system that includes a compensation circuit, a transconductance circuit, and an oscillator.

• The compensation circuit consists of a capacitor circuit and a resistive element. The resistance of the resistive element is determined by the center frequency of the PLL's bandwidth.

• The transconductance circuit includes a current source and an error amplifier. The current source generates a current based on the center frequency. The error amplifier has a transconductance that is also determined by the center frequency. It receives a signal that is dependent on the resistance and the difference between an input clock signal and a feedback signal.

• The oscillator, which is connected to the output of the error amplifier, generates a signal that is used to generate the feedback signal.

• The innovation in this patent application lies in the design of the compensation circuit, transconductance circuit, and oscillator, which work together to provide a stable and accurate phase locked loop system.

Abstract

In described examples, a phase locked loop (PLL) includes a compensation circuit, a transconductance circuit, and an oscillator. The compensation circuit includes a capacitor circuit and a resistive element having a resistance responsive to a center frequency of the PLL's bandwidth. The transconductance circuit includes a current source and an error amplifier. The current source generates a current responsive to the center frequency. The error amplifier has a transconductance responsive to the center frequency, and receives a signal responsive to the resistance and a difference between an input clock signal and a feedback signal. The oscillator input is coupled to the error amplifier output. The oscillator provides a signal at its output for generating the feedback signal.

ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING LINEARIZATION CIRCUIT WITH RECONFIGURABLE LOOKUP TABLE (LUT) MEMORY AND CALIBRATION OPTIONS (17825864)

Main Inventor

Narasimhan RAJAGOPAL

Brief explanation

The patent application describes a circuit that includes an analog-to-digital converter (ADC) and a linearization circuit.

• The ADC converts an analog input signal into a first digital output.
• The linearization circuit has a lookup table (LUT) memory that stores initial calibration data.
• The linearization circuit is connected to the ADC and performs the following functions:

 - Determines updated calibration data based on the initial calibration data.
 - Replaces the initial calibration data in the LUT memory with the updated calibration data.
 - Provides a second digital output at the linearization circuit output based on the first digital output and the updated calibration data.

Abstract

A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

ANALOG-TO-DIGITAL CONVERTER (ADC) HAVING SELECTIVE COMPARATOR OFFSET ERROR TRACKING AND RELATED CORRECTIONS (17828967)

Main Inventor

Viswanathan NAGARAJAN

Brief explanation

The patent application describes an analog-to-digital converter (ADC) that includes various components and features for improved accuracy and calibration.

• The ADC includes a set of comparators that compare an analog signal with reference thresholds to provide comparison results.
• Digitization circuitry then converts these comparison results into a digital output code using a mapping.
• The ADC also includes calibration circuitry to ensure accurate measurements.
• The calibration circuitry receives the comparison results and determines if the analog signal is close to any of the reference thresholds.
• If the analog signal is found to be close to a threshold, the calibration circuitry applies different pseudorandom binary sequence (PRBS) values to the analog signal and receives corresponding ADC values.
• Based on these ADC values, the calibration circuitry determines an offset error, which represents any deviation from the expected values.
• If the estimated offset error exceeds a predetermined threshold, the calibration circuitry provides a comparator input offset calibration signal at its output.
• This calibration signal can be used to adjust the ADC and compensate for any offset errors, thereby improving the accuracy of the conversion process.

Abstract

An analog-to-digital converter (ADC) includes: a set of comparators configured to provide comparison results based on an analog signal and respective reference thresholds for comparators of the set of comparators; digitization circuitry configured to provide a digital output code based on the comparison results and a mapping; and calibration circuitry. The calibration circuitry is configured to: receive the comparison results; determine if the analog signal is proximate to one of the respective reference thresholds based on the comparison results; in response to determining the analog signal is proximate to one of the respective reference thresholds, receive ADC values based on different pseudorandom binary sequence (PRBS) values being applied to the analog signal; determine an offset error based on the ADC values; and provide a comparator input offset calibration signal at a calibration circuitry output if the estimated offset error is greater than an offset error threshold.

ESTIMATION AND PRE-COMPENSATION OF HARMONIC COUPLING SPURS (17829218)

Main Inventor

Sarma Sundareswara GUNTURI

Brief explanation

The patent application describes a method for estimating and compensating for harmonic coupling in a transmitted signal.

• The method involves using a circuit to determine an estimated value of harmonic coupling in the transmitted signal.
• A feedback signal path is used to receive the transmitted signal and provide input for the estimation process.
• Based on the estimated value, pre-compensation is performed in the circuit to mitigate the effects of harmonic coupling.
• The goal of the method is to improve the quality and reliability of the transmitted signal by reducing the impact of harmonic coupling.

Abstract

Examples of this description provide for a method. In some examples, the method includes determining, via a circuit, an estimated value of harmonic coupling in a transmitted signal via a feedback signal path that receives the transmitted signal and performing pre-compensation for the harmonic coupling based on the estimated value, the pre-compensation performed in the circuit.

DIGITAL DISPLAY SYSTEM AND METHOD (18448205)

Main Inventor

Kristofer Scott OBERASCHER

Brief explanation

The patent application describes a system that includes a color filter and an integrator rod.

• The color filter has two segments, one that transmits light of a first color and reflects light of a second color, and another that does the opposite.
• The integrator rod is optically connected to the color filter.
• The system also includes a reflective surface with an aperture on one end of the integrator rod.

Abstract

A system includes a color filter including a first segment configured to transmit first light having a first color and to reflect second light having a second color and a second segment configured to transmit the second light having the second color and to reflect the first light having the first color. The system also includes an integrator rod optically coupled to the color filter, a reflective surface having an aperture on an end of the integrator rod.

INTEGRATED CIRCUIT WITH MULTI-APPLICATION IMAGE PROCESSING (18194249)

Main Inventor

Niraj Nandan

Brief explanation

The patent application describes an integrated circuit that includes multiple image processing blocks, data selection circuitry, and a pipeline memory.

• The integrated circuit has four image processing blocks, with each block receiving and processing image data.
• The output of the first image processing block is connected to the input of the second image processing block, creating a sequential processing flow.
• The output of the second image processing block is connected to the input of the third image processing block, continuing the sequential processing.
• The data selection circuitry has two inputs, one connected to the output of the first image processing block and the other connected to the output of the second image processing block.
• The data selection circuitry selects and outputs data from either the first or second image processing block.
• The output of the data selection circuitry is connected to the input of the pipeline memory, which stores the selected data.
• The output of the pipeline memory is connected to the input of the fourth image processing block, allowing further processing of the stored data.

Abstract

In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.

WIRELESS MANAGEMENT OF MODULAR SUBSYSTEMS WITH PROXY NODE OPTIONS (18232451)

Main Inventor

Ariton E. XHAFA

Brief explanation

- The patent application describes an integrated circuit designed for a wireless management system.

- The system consists of a primary node and multiple secondary nodes. - The integrated circuit includes a wireless transceiver and a wireless management controller. - The wireless management controller is responsible for managing the communication between the primary node and the secondary nodes. - The controller can identify a specific secondary node that is in communication with the primary node. - It can also identify another secondary node that is not in communication with the primary node. - The controller enables the first secondary node to act as a proxy node. - The proxy node can repeat downlink messages from the primary node to the second secondary node. - It can also repeat uplink messages from the second secondary node to the primary node. - This innovation allows for improved communication and coverage within the wireless management system.

Abstract

An integrated circuit for use in a wireless management system with a primary node and secondary nodes includes: a wireless transceiver; and a wireless management controller included with or coupled to the wireless transceiver. The wireless management controller is configured to: identify a first secondary node of the secondary nodes in communication with the primary node; identify a second secondary node of the secondary nodes not in communication with the primary node; and enable the first secondary node to operate as a proxy node that repeats downlink messages to or uplink messages from the second secondary node.

EFFICIENT UNICAST SUPER FRAME COMMUNICATIONS (17828895)

Main Inventor

Ariton E. XHAFA

Brief explanation

The patent application describes a vehicular battery management system (BMS) that includes a set of battery cells and a secondary network node connected to these cells.

• The secondary network node can wirelessly receive a specific type of data packet called a unicast downlink packet from a primary network node in a designated time slot.
• The unicast downlink packet is specifically addressed to the secondary network node.
• The secondary network node can also wirelessly transmit an uplink packet to the primary network node in a different time slot, in response to the received unicast downlink packet.
• This system allows for wireless communication between the primary and secondary network nodes, enabling efficient battery management in vehicles.

Abstract

In some examples, a vehicular battery management system (BMS) comprises a set of battery cells and a secondary network node coupled to the set of battery cells. The secondary network node is configured to wirelessly receive, in a first slot of a super frame, a unicast downlink packet from a primary network node, the unicast downlink packet addressed to the secondary network node. The secondary network node is also configured to wirelessly transmit, in a second slot of the super frame and responsive to the unicast downlink packet, an uplink packet to the primary network node.

FREQUENCY CHANGE DURING CONNECTION EVENT (17828225)

Main Inventor

Yaron Alpert

Brief explanation

The abstract describes a method in a communication system where a first node sends a request to change the operation frequency to a second node during a connection event. The request is encoded in a first operation frequency. The first node also sends a packet to the second node during the same connection event, and this packet is encoded in a second operation frequency, which is different from the first operation frequency.

• The method involves communication between two nodes in a system.
• The first node sends a request to the second node to change the operation frequency during a connection event.
• The request is encoded in a specific operation frequency.
• The first node also sends a packet to the second node during the same connection event.
• The packet is encoded in a different operation frequency than the request.
• The purpose of the method is to enable frequency changes and communication between nodes in a communication system.

Abstract

A method includes sending, by a first node to a second node during a first connection event, a request to change a current operation frequency, wherein the request is encoded in a first operation frequency. The method also includes sending, by the first node to the second node during the first connection event, a first packet encoded in a second operation frequency, where second operation frequency is different from the first operation frequency.