US Patent Application 18175333. DATA PROCESSING PIPELINE simplified abstract

DATA PROCESSING PIPELINE

Organization Name

TEXAS INSTRUMENTS INCORPORATED

Inventor(s)

Mihir Mody of Bangalore (IN)

Niraj Nandan of Plano TX (US)

Rajasekhar Allu of Plano TX (US)

Ankur Ankur of Bangalore (IN)

DATA PROCESSING PIPELINE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18175333 titled 'DATA PROCESSING PIPELINE

Simplified Explanation

The patent application describes a data processing device that includes multiple hardware accelerators, a scheduler circuit, and a blocking circuit.

• The data processing device has hardware accelerators, which are specialized circuits designed to perform specific tasks quickly.
• The scheduler circuit is connected to the hardware accelerators and consists of multiple hardware task schedulers.
• Each hardware task scheduler is linked to a specific hardware accelerator and controls the execution of tasks by that accelerator.
• The blocking circuit is also connected to the hardware accelerators and is designed to prevent communication between two specific hardware accelerators.
• The purpose of the blocking circuit is to restrict the interaction between certain hardware accelerators, possibly to avoid conflicts or optimize performance.

Original Abstract Submitted

A data processing device includes a plurality of hardware accelerators, a scheduler circuit, and a blocking circuit. The scheduler circuit is coupled to the plurality of hardware accelerators, and includes a plurality of hardware task schedulers. Each hardware task scheduler is coupled to a corresponding hardware accelerator, and is configured to control execution of the task by the hardware accelerator. The blocking circuit is coupled to the plurality of hardware accelerators and configured to inhibit communication between a first hardware accelerator and a second hardware accelerator of the plurality of hardware task schedulers.