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| − | ==Patent applications for Texas Instruments Incorporated on December 28th, 2023==
| + | '''Summary of the patent applications from Texas Instruments Incorporated on December 28th, 2023''' |
| − | | |
| − | ===METHODS AND APPARATUS TO ESTIMATE CABLE LENGTH ([[18072458. METHODS AND APPARATUS TO ESTIMATE CABLE LENGTH simplified abstract (Texas Instruments Incorporated)|18072458]])===
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| | + | Texas Instruments Incorporated has recently filed several patents related to improving wireless communication, image compression, video decoding, and power line communication. These patents aim to enhance the performance, reliability, and efficiency of various technologies and systems. |
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| − | '''Main Inventor'''
| + | In wireless communication, one patent focuses on improving Wi-Fi communication by using multiple antennas and feedback. This method allows for better signal strength, range, and overall performance, as well as adaptability to changing Wi-Fi conditions and interference. Another patent addresses efficient transmission of downlink control information in a wireless transmission system, improving wireless communication performance and signal quality. |
| | | | |
| − | Raghu Ganesan
| + | In the field of image compression, a patent describes a method that utilizes variable length entropy codes and spatial prediction to compress digital image data. This method offers higher compression ratios, improved image quality preservation, and faster encoding and decoding processes. |
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| | + | For video decoding, a patent introduces a method for parallel decoding of independently encoded sub-pictures in a compressed video bit stream. This leads to faster and more efficient video decoding, improved video quality, and reduced latency in video processing and playback. |
| | | | |
| − | '''Brief explanation'''
| + | In power line communication, one patent presents an algorithm that promotes terminal nodes to switch nodes, reducing network overhead, collisions, and the number of levels in the network. This algorithm improves the efficiency and performance of power line communication systems, making them more suitable for applications such as smart grid systems and home automation. |
| − | The abstract describes a patent application for a device that can estimate the length of a cable used for communication. The device includes various circuitry components to establish cable communication, sample cable voltages, determine echo coefficients, and estimate the cable length.
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| − | * The device includes processor circuitry to establish cable communication.
| + | Notable applications of these patents include improving Wi-Fi performance and reliability in various environments, enhancing wireless communication in IoT devices, efficient encoding and decoding of digital images, optimizing video decoding performance and speed, and enhancing the efficiency and reliability of power line communication systems. |
| − | * It also includes analog to digital converter circuitry to sample cable voltages over time.
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| − | * Echo estimator circuitry is included to determine echo coefficients corresponding to the sampled voltages.
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| − | * Physical length estimator circuitry is included to identify specific echo coefficients and estimate the cable length based on these coefficients.
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| − | == Potential Applications ==
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| − | * This technology can be used in various industries that rely on cable communication, such as telecommunications, networking, and audio/video systems.
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| − | * It can be applied in the installation and maintenance of cable systems to accurately determine the length of cables required.
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| − | == Problems Solved ==
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| − | * Accurately estimating the length of a cable can be challenging, especially in situations where the cable is already installed or when there are multiple echoes.
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| − | * This technology solves the problem of estimating cable length by utilizing echo coefficients and specific thresholds to identify near end and far end echoes.
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| | | | |
| − | == Benefits ==
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| − | * The device provides a simplified and efficient method for estimating cable length.
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| − | * It eliminates the need for manual measurements or complex calculations.
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| − | * Accurate cable length estimation can lead to cost savings in cable installations and maintenance.
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| | | | |
| − | '''Abstract'''
| + | ==Patent applications for Texas Instruments Incorporated on December 28th, 2023== |
| − | An example first device includes: processor circuitry configured to establish a cable communication; analog to digital converter circuitry configured to sample cable voltages over time; echo estimator circuitry configured to determine a plurality of echo coefficients corresponding to the plurality of voltages; and physical length estimator circuitry configured to: identify a first echo coefficient in the echo coefficients that satisfies a static threshold, the first echo coefficient corresponding to a near end echo; identify a second echo coefficient in the echo coefficients that satisfies a dynamic threshold, the second echo coefficient corresponding to a far end echo; and estimate the length of a cable for the cable communication based on the first echo coefficient and the second echo coefficient.
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| − | ===METHOD FOR MEASURING QUIESCENT CURRENT IN A SWITCHING VOLTAGE REGULATOR ([[17846397. METHOD FOR MEASURING QUIESCENT CURRENT IN A SWITCHING VOLTAGE REGULATOR simplified abstract (Texas Instruments Incorporated)|17846397]])=== | + | ===METHODS AND APPARATUS TO ESTIMATE CABLE LENGTH ([[18072458. METHODS AND APPARATUS TO ESTIMATE CABLE LENGTH simplified abstract (Texas Instruments Incorporated)|18072458]])=== |
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| | '''Main Inventor''' | | '''Main Inventor''' |
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| − | HARSH PATEL
| + | Raghu Ganesan |
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| | | | |
| − | '''Brief explanation'''
| + | ===METHOD FOR MEASURING QUIESCENT CURRENT IN A SWITCHING VOLTAGE REGULATOR ([[17846397. METHOD FOR MEASURING QUIESCENT CURRENT IN A SWITCHING VOLTAGE REGULATOR simplified abstract (Texas Instruments Incorporated)|17846397]])=== |
| − | The abstract describes a method for measuring the quiescent current in a switching voltage regulator. The method involves generating a mathematical model of the circuit design, fabricating a circuit based on the design, and measuring the parameters of the circuit to calculate the switching current and quiescent current.
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| − | * The method involves generating a mathematical model of a circuit design associated with a switching voltage regulator.
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| − | * The mathematical model includes measurable parameters that describe the switching current of a power switch in the regulator.
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| − | * A circuit is fabricated based on the circuit design, including the power switch and conductive I/O.
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| − | * The conductive I/O of the fabricated circuit is coupled to a circuit test fixture.
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| − | * Electrical signals are provided to the conductive I/O via the test fixture.
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| − | * The measurable parameters are measured in response to the electrical signals.
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| − | * The measurable parameters are applied to the mathematical model to calculate the switching current.
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| − | * The quiescent current is then calculated based on the switching current.
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| − | == Potential Applications ==
| + | '''Main Inventor''' |
| − | * This method can be applied in the field of power electronics for measuring the quiescent current in switching voltage regulators.
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| − | * It can be used in the design and testing of switching voltage regulators to ensure their efficiency and performance.
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| | | | |
| − | == Problems Solved ==
| + | HARSH PATEL |
| − | * The method solves the problem of accurately measuring the quiescent current in a switching voltage regulator.
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| − | * It provides a reliable and efficient way to calculate the switching current and quiescent current of the regulator.
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| | | | |
| − | == Benefits ==
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| − | * The method allows for accurate measurement and calculation of the switching current and quiescent current in a switching voltage regulator.
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| − | * It provides a cost-effective and time-efficient solution for testing and evaluating the performance of regulators.
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| − | * By accurately measuring the quiescent current, it helps in optimizing the design and efficiency of switching voltage regulators.
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| − |
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| − | '''Abstract'''
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| − | One example includes a method for measuring a quiescent current in a switching voltage regulator. The method includes generating a mathematical model of a circuit design associated with the switching voltage regulator. The mathematical model includes measurable parameters to describe a switching current of a power switch of the switching voltage regulator. The method also includes fabricating a circuit comprising the switching voltage regulator based on the circuit design. The fabricated circuit includes the power switch and conductive I/O. The method also includes coupling the conductive I/O of the fabricated circuit to a circuit test fixture and providing electrical signals to the conductive I/O via the circuit test fixture. The method also includes measuring the measurable parameters in response to the electrical signals and applying the measurable parameters to the mathematical model to calculate the switching current. The method further includes calculating the quiescent current based on the switching current.
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| | ===3D TAP & SCAN PORT ARCHITECTURES ([[18368195. 3D TAP & SCAN PORT ARCHITECTURES simplified abstract (Texas Instruments Incorporated)|18368195]])=== | | ===3D TAP & SCAN PORT ARCHITECTURES ([[18368195. 3D TAP & SCAN PORT ARCHITECTURES simplified abstract (Texas Instruments Incorporated)|18368195]])=== |
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| | Lee D. Whetsel | | Lee D. Whetsel |
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| − | '''Brief explanation'''
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| − | The abstract of this patent application describes the implementation of die test architectures in a die stack, specifically in the first, middle, and last die. These architectures are mostly the same, with a few exceptions mentioned in the disclosure.
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| − |
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| − | * Die test architectures implemented in a die stack
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| − | * Specifically designed for the first, middle, and last die
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| − | * Architectures are mostly the same with a few exceptions
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| − | * Described in detail in the disclosure section of the patent application
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| − |
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| − | ==Potential Applications==
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| − | * Semiconductor manufacturing industry
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| − | * Die stacking technology
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| − | * Testing and quality control of die stacks
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| − |
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| − | ==Problems Solved==
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| − | * Standardizing die test architectures in a die stack
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| − | * Ensuring consistent testing procedures across different dies
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| − | * Addressing any exceptions or variations in the test architectures
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| − |
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| − | ==Benefits==
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| − | * Improved efficiency in die testing
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| − | * Streamlined testing procedures for die stacks
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| − | * Enhanced quality control measures for die stacks
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| − |
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| − | '''Abstract'''
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| − | This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.
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| | | | |
| | ===GATED RING OSCILLATOR LINEARIZATION ([[18466027. GATED RING OSCILLATOR LINEARIZATION simplified abstract (Texas Instruments Incorporated)|18466027]])=== | | ===GATED RING OSCILLATOR LINEARIZATION ([[18466027. GATED RING OSCILLATOR LINEARIZATION simplified abstract (Texas Instruments Incorporated)|18466027]])=== |
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| | Marius MOE | | Marius MOE |
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| − | '''Brief explanation'''
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| − | The patent application describes an apparatus that includes a time-to-digital converter (TDC) and a processor. The TDC receives a signal and measures the time between start and stop events of the signal. The processor compares the measurement result to a target value and determines a non-linearity model to correct any variance from the target value.
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| − |
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| − | * The apparatus includes a time-to-digital converter (TDC) and a processor.
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| − | * The TDC receives a signal and measures the time between start and stop events of the signal.
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| − | * The processor compares the measurement result to a target value.
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| − | * The processor determines a non-linearity model to correct any variance from the target value.
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| − |
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| − | == Potential Applications ==
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| − | This technology could have various potential applications, including:
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| − |
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| − | * High-precision time measurement in scientific experiments.
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| − | * Timing synchronization in telecommunications networks.
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| − | * Distance measurement in radar or lidar systems.
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| − | * Time-of-flight measurements in range finding devices.
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| − |
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| − | == Problems Solved ==
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| − | The technology addresses the following problems:
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| − |
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| − | * Variance in time measurement results obtained from a signal.
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| − | * Non-linearity in the measurement results.
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| − | * Need for accurate and precise time measurements.
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| − |
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| − | == Benefits ==
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| − | The technology offers several benefits, such as:
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| − |
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| − | * Improved accuracy and precision in time measurements.
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| − | * Correcting non-linearity in measurement results.
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| − | * Enhancing the reliability of timing synchronization.
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| − | * Enabling more accurate distance and range measurements.
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| − |
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| − | '''Abstract'''
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| − | Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.
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| | ===FAST POWER-UP SCHEME FOR CURRENT MIRRORS ([[17966253. FAST POWER-UP SCHEME FOR CURRENT MIRRORS simplified abstract (Texas Instruments Incorporated)|17966253]])=== | | ===FAST POWER-UP SCHEME FOR CURRENT MIRRORS ([[17966253. FAST POWER-UP SCHEME FOR CURRENT MIRRORS simplified abstract (Texas Instruments Incorporated)|17966253]])=== |
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| | Saurabh Pandey | | Saurabh Pandey |
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| − |
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| − | '''Brief explanation'''
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| − | '''Abstract:'''
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| − | The patent application describes an automatic charge/discharge circuit that enables a current mirror circuit with a high capacitance to rapidly and automatically charge or discharge the capacitance, facilitating a quick start-up power supply. The circuit is designed to cease charging or discharging when the voltage on the capacitance reaches a desired steady state.
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| − |
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| − | '''Patent/Innovation Explanation:'''
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| − | * The invention is an automatic charge/discharge circuit.
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| − | * It is specifically designed for a current mirror circuit with a high capacitance.
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| − | * The circuit allows for quick and automatic charging or discharging of the capacitance.
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| − | * It ensures that the charging or discharging process stops when the voltage on the capacitance reaches a desired steady state.
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| − |
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| − | '''Potential Applications:'''
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| − | * Fast start-up power supplies
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| − | * High-capacitance current mirror circuits
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| − |
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| − | '''Problems Solved:'''
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| − | * Slow charging or discharging of high-capacitance circuits
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| − | * Manual intervention required to stop the charging or discharging process
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| − |
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| − | '''Benefits:'''
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| − | * Rapid charging or discharging of the capacitance
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| − | * Automatic control of the charging or discharging process
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| − | * Elimination of the need for manual intervention
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| − |
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| − | '''Abstract'''
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| − | An automatic charge/discharge circuit is presented that allows a current mirror circuit with a high capacitance to quickly and automatically charge or discharge the capacitance in order to allow for a fast start-up power supply. The charge/discharge circuit automatically stops charging or discharging as the voltage on the capacitance approached a desired steady state.
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| | ===MULTICORE SHARED CACHE OPERATION ENGINE ([[18243809. MULTICORE SHARED CACHE OPERATION ENGINE simplified abstract (Texas Instruments Incorporated)|18243809]])=== | | ===MULTICORE SHARED CACHE OPERATION ENGINE ([[18243809. MULTICORE SHARED CACHE OPERATION ENGINE simplified abstract (Texas Instruments Incorporated)|18243809]])=== |
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| | Kai Chirca | | Kai Chirca |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract of this patent application describes a technique for managing memory in a system based on triggering events. Here is a simplified explanation of the abstract:
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| − |
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| − | * The technique involves receiving configuration information for a trigger control channel, which defines one or more triggering events.
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| − | * A first memory management command is received and stored.
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| − | * The system then detects the occurrence of one or more triggering events.
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| − | * Based on the detected triggering events, the stored memory management command is triggered.
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| − |
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| − | Potential applications of this technology:
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| − |
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| − | * This technique can be applied in computer systems or electronic devices that require efficient memory management.
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| − | * It can be used in systems where certain actions need to be triggered based on specific events.
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| − |
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| − | Problems solved by this technology:
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| − |
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| − | * This technique solves the problem of manual memory management by automating the process based on predefined triggering events.
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| − | * It helps in optimizing memory usage and improving system performance.
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| − |
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| − | Benefits of this technology:
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| − | * By automating memory management, this technique reduces the burden on system administrators or users.
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| − | * It ensures that memory management commands are executed at the appropriate time, leading to improved efficiency.
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| − | * The technique allows for more precise control over memory usage, resulting in better resource allocation.
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| − |
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| − | '''Abstract'''
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| − | Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.
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| | ===METHODS AND APPARATUS TO SCHEDULE MEMORY OPERATIONS ([[17848159. METHODS AND APPARATUS TO SCHEDULE MEMORY OPERATIONS simplified abstract (Texas Instruments Incorporated)|17848159]])=== | | ===METHODS AND APPARATUS TO SCHEDULE MEMORY OPERATIONS ([[17848159. METHODS AND APPARATUS TO SCHEDULE MEMORY OPERATIONS simplified abstract (Texas Instruments Incorporated)|17848159]])=== |
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| | Vignesh Raghavendra | | Vignesh Raghavendra |
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| − | '''Brief explanation'''
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| − | The abstract describes a device that includes a compute core, flash manager circuitry, and flash memory. The compute core sends a request to the flash manager circuitry to store write data in the flash memory, and then sends another request to transfer a read operation to the flash memory. The flash manager circuitry receives the requests and determines whether to preempt the storing of the write data in order to transmit the read operation to the flash memory. The flash memory provides data to the compute core based on the transmitted read operation.
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| − |
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| − | * The device includes a compute core, flash manager circuitry, and flash memory.
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| − | * The compute core sends a request to store write data in the flash memory.
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| − | * The compute core also sends a request to transfer a read operation to the flash memory.
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| − | * The flash manager circuitry receives the requests from the compute core.
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| − | * The flash manager circuitry determines whether to preempt the storing of the write data.
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| − | * If preempted, the flash manager circuitry transmits the read operation to the flash memory.
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| − | * The flash memory provides data to the compute core based on the transmitted read operation.
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| − |
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| − | == Potential Applications ==
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| − | * This technology can be used in devices that require efficient storage and retrieval of data, such as smartphones, tablets, and IoT devices.
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| − | * It can be applied in systems that need to perform simultaneous read and write operations on flash memory.
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| − |
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| − | == Problems Solved ==
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| − | * The device solves the problem of efficiently managing read and write operations on flash memory.
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| − | * It addresses the issue of potential conflicts between storing write data and performing read operations.
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| − |
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| − | == Benefits ==
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| − | * The device allows for concurrent read and write operations on flash memory, improving overall system performance.
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| − | * It reduces the need for multiple memory accesses, leading to faster data retrieval.
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| − | * The technology provides a more efficient and streamlined approach to managing flash memory operations.
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| − |
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| − | '''Abstract'''
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| − | An example device includes: a compute core configured to: send a first request to flash manager circuitry, the first request to store write data in a flash memory; and send a second request to the flash manager circuitry, the second request sent after the first request, the second request to transfer an XIP read operation to the flash memory; the flash manager circuitry configured to: receive the first request; transmit the write data to the flash memory for storing in the flash memory; receive the second request before the storing of the write data is complete; determine whether to preempt the storing of the write data, transmit, in response to a determination to preempt, the XIP read operation to the flash; and the flash memory configured to provide data to the compute core based on the transmitted XIP read operation.
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| | ===BITONIC SORTING ACCELERATOR ([[18335452. BITONIC SORTING ACCELERATOR simplified abstract (Texas Instruments Incorporated)|18335452]])=== | | ===BITONIC SORTING ACCELERATOR ([[18335452. BITONIC SORTING ACCELERATOR simplified abstract (Texas Instruments Incorporated)|18335452]])=== |
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| | Indu Prathapan | | Indu Prathapan |
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| − | '''Brief explanation'''
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| − | The abstract describes an accelerator for bitonic sorting, which is a sorting algorithm used in parallel computing systems. The accelerator includes multiple compare-exchange circuits and a FIFO buffer associated with each circuit.
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| − |
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| − | * The compare-exchange circuits perform comparisons and exchanges between values in the FIFO buffers.
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| − | * In the first mode, the circuit stores a previous value from a previous circuit or memory to its FIFO buffer and passes a FIFO value to the next circuit or memory.
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| − | * In the second mode, the circuit compares the previous value with the FIFO value, stores the greater value in its FIFO buffer, and passes the lesser value to the next circuit or memory.
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| − | * In the third mode, the circuit compares the previous value with the FIFO value, stores the lesser value in its FIFO buffer, and passes the greater value to the next circuit or memory.
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| − |
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| − | Potential applications of this technology:
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| − | * Parallel computing systems that require efficient sorting algorithms.
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| − | * High-performance computing applications that involve large datasets.
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| − |
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| − | Problems solved by this technology:
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| − | * Efficient sorting of data in parallel computing systems.
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| − | * Reducing the complexity and latency of sorting algorithms.
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| − | Benefits of this technology:
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| − |
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| − | * Improved performance and efficiency in sorting large datasets.
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| − | * Simplified implementation of bitonic sorting algorithms.
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| − | * Reduced latency in parallel computing systems.
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| − |
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| − | '''Abstract'''
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| − | An accelerator for bitonic sorting includes a plurality of compare-exchange circuits and a first-in, first-out (FIFO) buffer associated with each of the compare-exchange circuits. An output of each FIFO buffer is a FIFO value. The compare-exchange circuits are configured to, in a first mode, store a previous value from a previous compare-exchange circuit or a memory to its associated FIFO buffer and pass a FIFO value from its associated FIFO buffer to a subsequent compare-exchange circuit or the memory; in a second mode, compare the previous value to the FIFO value, store the greater value to its associated FIFO buffer, and pass the lesser value to the subsequent compare-exchange circuit or the memory; and in a third mode, compare the previous value to the FIFO value, store the lesser value to its associated FIFO buffer, and pass the greater value to the subsequent compare-exchange circuit or the memory.
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| | ===LIVE FIRMWARE UPDATE SWITCHOVER ([[18463515. LIVE FIRMWARE UPDATE SWITCHOVER simplified abstract (Texas Instruments Incorporated)|18463515]])=== | | ===LIVE FIRMWARE UPDATE SWITCHOVER ([[18463515. LIVE FIRMWARE UPDATE SWITCHOVER simplified abstract (Texas Instruments Incorporated)|18463515]])=== |
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| | Sira Parasurama Rao | | Sira Parasurama Rao |
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| − | '''Brief explanation'''
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| − | The abstract describes a method for updating firmware in a microcontroller. Here is a simplified explanation:
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| − |
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| − | * The method involves receiving a command from an external host to update the firmware of a microcontroller.
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| − | * The microcontroller then downloads an image of a new version of the firmware in response to the command.
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| − | * During a first time period, the method initializes only the variables that are present in the new version but not in the old version of the firmware.
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| − | * During a second time period, the method updates certain elements like the interrupt vector table, function pointer, and stack pointer based on the new version.
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| − | * The second time period starts after the initialization of the variables is completed.
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| − |
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| − | Potential applications of this technology:
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| − |
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| − | * This method can be used in various devices that utilize microcontrollers, such as IoT devices, embedded systems, and consumer electronics.
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| − | * It can be particularly useful in situations where firmware updates need to be performed remotely or in real-time.
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| − |
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| − | Problems solved by this technology:
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| − |
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| − | * The method allows for efficient and streamlined firmware updates by only initializing the necessary variables and updating specific elements.
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| − | * It eliminates the need to update the entire firmware, saving time and resources.
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| − |
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| − | Benefits of this technology:
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| − |
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| − | * The method enables quick and targeted firmware updates, reducing downtime and improving device performance.
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| − | * It provides flexibility in updating firmware, allowing for incremental updates without disrupting the entire system.
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| − | * The ability to update firmware remotely enhances convenience and reduces the need for physical access to devices.
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| − |
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| − | '''Abstract'''
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| − | A method includes receiving, by a microcontroller, a live firmware update (LFU) command from an external host; and downloading, by the microcontroller, an image of a new version of firmware responsive to the LFU command. During a first time period, the method includes initializing only variables contained in the new version that are not contained in an old version of firmware. During a second time period, the method includes updating one or more of an interrupt vector table, a function pointer, and/or a stack pointer responsive to the new version. The second time period begins responsive to completing initialization of the variables.
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| | ===VECTOR LOAD AND DUPLICATE OPERATIONS ([[18243326. VECTOR LOAD AND DUPLICATE OPERATIONS simplified abstract (Texas Instruments Incorporated)|18243326]])=== | | ===VECTOR LOAD AND DUPLICATE OPERATIONS ([[18243326. VECTOR LOAD AND DUPLICATE OPERATIONS simplified abstract (Texas Instruments Incorporated)|18243326]])=== |
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| | Timothy David Anderson | | Timothy David Anderson |
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| − |
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| − | '''Brief explanation'''
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| − | The disclosed embodiments of this patent application describe methods for using a processor to load and duplicate scalar data from a source into a destination register. The duplication can be done in byte, half word, word, or double word parts, based on a duplication pattern.
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| − |
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| − | * The patent application focuses on methods of loading and duplicating scalar data from a source to a destination register using a processor.
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| − | * The data duplication can be done in different parts, such as byte, half word, word, or double word, based on a specific duplication pattern.
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| − | * The disclosed embodiments provide a detailed explanation of the process and techniques involved in duplicating scalar data.
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| − | * The patent application may include specific algorithms or instructions for the processor to perform the data duplication.
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| − | * The methods described in the patent application can be implemented in various computer systems or processors.
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| − |
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| − | == Potential Applications ==
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| − | * This technology can be applied in computer processors or systems that require efficient data duplication.
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| − | * It can be used in applications that involve data processing, such as image or video processing, where duplicating data in different parts is necessary.
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| − | * The methods described in the patent application can be utilized in programming languages or compilers to optimize data duplication operations.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * The patent application addresses the problem of efficiently duplicating scalar data from a source to a destination register.
| |
| − | * It provides a solution for duplicating data in different parts, such as byte, half word, word, or double word, based on a specific pattern.
| |
| − | * The disclosed methods can improve the performance and efficiency of data duplication operations in computer systems or processors.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * The technology described in the patent application allows for efficient and optimized data duplication in computer systems or processors.
| |
| − | * It provides flexibility in duplicating data in different parts, based on specific patterns, which can be beneficial in various applications.
| |
| − | * The methods described in the patent application can potentially improve the overall performance and speed of data processing operations.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Disclosed embodiments relate to methods of using a processor to load and duplicate scalar data from a source into a destination register. The data may be duplicated in byte, half word, word or double word parts, according to a duplication pattern.
| |
| | | | |
| | ===MONITORING TRANSITIONS OF A CIRCUIT ([[18465213. MONITORING TRANSITIONS OF A CIRCUIT simplified abstract (Texas Instruments Incorporated)|18465213]])=== | | ===MONITORING TRANSITIONS OF A CIRCUIT ([[18465213. MONITORING TRANSITIONS OF A CIRCUIT simplified abstract (Texas Instruments Incorporated)|18465213]])=== |
| Line 362: |
Line 105: |
| | RONALD NERLICH | | RONALD NERLICH |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a circuit that includes several interconnected components for triggering a reset signal based on certain input signals and a clock signal.
| |
| − |
| |
| − | * The circuit includes a guard trigger circuit with two input nodes and an output node. The input nodes are connected to state signals, and the output node provides a trigger signal.
| |
| − | * A reset synchronizer circuit is also included, which takes the trigger signal from the guard trigger circuit as input, along with a clock signal. It produces an output signal.
| |
| − | * A timeout circuit is part of the circuit as well, taking the output signal from the reset synchronizer circuit and the clock signal as inputs. It generates an output signal.
| |
| − | * Finally, a reset requestor circuit is included, which takes the trigger signal from the guard trigger circuit and the output signal from the timeout circuit as inputs.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * This circuit can be used in electronic devices that require a reset signal to be triggered based on certain conditions or events.
| |
| − | * It can be implemented in various systems where synchronization and timing are crucial, such as communication systems, control systems, or data processing systems.
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * The circuit provides a reliable and efficient way to trigger a reset signal based on specific input conditions and timing requirements.
| |
| − | * It ensures that the reset signal is synchronized with the clock signal, preventing any timing issues or glitches.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * The circuit offers a robust and accurate mechanism for triggering a reset signal, enhancing the overall reliability and performance of electronic devices.
| |
| − | * It allows for precise control over the timing of the reset signal, ensuring that it is triggered at the desired moment.
| |
| − | * The circuit can be easily integrated into existing electronic systems, providing a flexible and adaptable solution.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A circuit includes a guard trigger circuit that includes a first input node adapted to be coupled to a first state signal, a second input node adapted to be coupled to a second state signal and an output node. The circuit also includes a reset synchronizer circuit that includes an input node coupled to the output node of the guard trigger circuit, a clock node adapted to be coupled to a clock signal and an output node. The circuit further includes a timeout circuit including an input node coupled to the output node of the reset synchronizer circuit, a clock node adapted to be coupled to the clock signal and an output node. The circuit still further includes a reset requestor circuit that includes a first input node coupled to the output node of the guard trigger circuit, a second node coupled to the output node of the timeout circuit.
| |
| | | | |
| | ===DEBUG FOR MULTI-THREADED PROCESSING ([[18243421. DEBUG FOR MULTI-THREADED PROCESSING simplified abstract (Texas Instruments Incorporated)|18243421]])=== | | ===DEBUG FOR MULTI-THREADED PROCESSING ([[18243421. DEBUG FOR MULTI-THREADED PROCESSING simplified abstract (Texas Instruments Incorporated)|18243421]])=== |
| Line 397: |
Line 113: |
| | NIRAJ NANDAN | | NIRAJ NANDAN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a system for implementing debugging in a multi-threaded processor. The system includes a hardware thread scheduler, multiple schedulers for processing instructions, a debug control, and hardware accelerators.
| |
| − |
| |
| − | * The system includes a hardware thread scheduler that schedules the processing of data.
| |
| − | * Multiple schedulers are present, each responsible for scheduling a specific pipeline for processing instructions.
| |
| − | * A debug control is included to control the schedulers, allowing them to halt, step, or resume the processing of data for debugging purposes.
| |
| − | * The system also includes multiple hardware accelerators that execute instructions for a given pipeline based on a schedule provided by a scheduler.
| |
| − | * Each hardware accelerator is connected to at least one scheduler and a shared memory.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * Debugging multi-threaded processors.
| |
| − | * Improving the efficiency and performance of multi-threaded processors.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * Debugging complex multi-threaded processors can be challenging. This system provides a solution by allowing for the control and monitoring of individual pipelines for debugging purposes.
| |
| − | * The system also helps in improving the overall efficiency and performance of multi-threaded processors by utilizing hardware accelerators and optimized scheduling.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * Enhanced debugging capabilities for multi-threaded processors.
| |
| − | * Improved efficiency and performance of multi-threaded processors.
| |
| − | * Better control and monitoring of individual pipelines for debugging purposes.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A system to implement debugging for a multi-threaded processor is provided. The system includes a hardware thread scheduler configured to schedule processing of data, and a plurality of schedulers, each configured to schedule a given pipeline for processing instructions. The system further includes a debug control configured to control at least one of the plurality of schedulers to halt, step, or resume the given pipeline of the at least one of the plurality of schedulers for the data to enable debugging thereof. The system further includes a plurality of hardware accelerators configured to implement a series of tasks in accordance with a schedule provided by a respective scheduler in accordance with a command from the debug control. Each of the plurality of hardware accelerators is coupled to at least one of the plurality of schedulers to execute the instructions for the given pipeline and to a shared memory.
| |
| | | | |
| | ===SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS ([[18463101. SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS simplified abstract (Texas Instruments Incorporated)|18463101]])=== | | ===SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS ([[18463101. SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS simplified abstract (Texas Instruments Incorporated)|18463101]])=== |
| Line 430: |
Line 121: |
| | Kai CHIRCA | | Kai CHIRCA |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a prefetch unit with multiple memories and a memory controller. The memory controller includes a prefetch stream filter and a prefetch buffer. The prefetch stream filter has address slots and direction prediction fields associated with each address slot. The prefetch buffer has buffer slots with various fields for storing data.
| |
| − |
| |
| − | * The prefetch unit has multiple memories and a memory controller.
| |
| − | * The memory controller includes a prefetch stream filter and a prefetch buffer.
| |
| − | * The prefetch stream filter has address slots and direction prediction fields.
| |
| − | * Each address slot in the prefetch stream filter is associated with a direction prediction field.
| |
| − | * The prefetch buffer has buffer slots with various fields for storing data.
| |
| − | * Each buffer slot in the prefetch buffer has an address field, direction prediction field, data pending field, data valid field, and sub-slots for storing data.
| |
| − | * The address field in each buffer slot stores at least a portion of the corresponding address.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Computer processors and systems that require efficient memory access.
| |
| − | * High-performance computing applications that rely on prefetching data.
| |
| − | * Data-intensive tasks such as machine learning, data analytics, and simulations.
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Improves memory access efficiency by prefetching data.
| |
| − | * Reduces memory latency by predicting memory access patterns.
| |
| − | * Optimizes data retrieval and processing in memory-intensive applications.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Faster data access and processing.
| |
| − | * Improved overall system performance.
| |
| − | * Enhanced efficiency in memory-intensive tasks.
| |
| − | * Reduced memory latency and improved responsiveness.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A prefetch unit includes multiple memories; and a memory controller coupled to the multiple memories. The memory controller includes a prefetch stream filter and a prefetch buffer. The prefetch stream filter includes a first set of address slots and a set of direction prediction fields, each of which is associated with a respective one of the address slots of the first set of address slots. The prefetch buffer includes a set of buffer slots, each slot of the set of buffer slots including an address field, a direction prediction field, a data pending field, a data valid field, and a set of sub-slots configured to store data, wherein each address field of each slot of the set of buffer slots is configured to store at least a portion of an address associated with the corresponding slot.
| |
| | | | |
| | ===TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EXECUTION ([[18460772. TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EXECUTION simplified abstract (Texas Instruments Incorporated)|18460772]])=== | | ===TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EXECUTION ([[18460772. TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EXECUTION simplified abstract (Texas Instruments Incorporated)|18460772]])=== |
| Line 471: |
Line 129: |
| | Duc Quang Bui | | Duc Quang Bui |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract of the patent application describes a method for operating a computer system using an instruction loop executed by a processor. The loop accesses a current data vector and its associated vector predicate. The loop is repeated as long as the current data vector contains valid data elements, and it is exited when the current data vector contains no valid data elements.
| |
| − |
| |
| − | * The method involves executing an instruction loop on a computer system.
| |
| − | * Each iteration of the loop accesses a current data vector and its associated vector predicate.
| |
| − | * The loop continues as long as the current data vector contains at least one valid data element.
| |
| − | * The loop is exited when the current data vector contains no valid data elements.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * This method can be used in various computer systems and applications that require processing data vectors.
| |
| − | * It can be applied in data analysis, machine learning, and artificial intelligence algorithms.
| |
| − | * It can be used in real-time systems where efficient processing of data vectors is crucial.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * The method solves the problem of efficiently processing data vectors by using a loop that checks the validity of data elements.
| |
| − | * It ensures that only valid data elements are processed, improving the accuracy and efficiency of the system.
| |
| − | * The method provides a mechanism to exit the loop when no valid data elements are present, saving computational resources.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * Improved efficiency and accuracy in processing data vectors.
| |
| − | * Reduction in computational resources by exiting the loop when no valid data elements are present.
| |
| − | * Increased flexibility in handling different types of data vectors and their associated predicates.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | In a method of operating a computer system, an instruction loop is executed by a processor in which each iteration of the instruction loop accesses a current data vector and an associated current vector predicate. The instruction loop is repeated when the current vector predicate indicates the current data vector contains at least one valid data element and the instruction loop is exited when the current vector predicate indicates the current data vector contains no valid data elements.
| |
| | | | |
| | ===ERROR HANDLING IN A GEOMETRIC CORRECTION ENGINE ([[18465250. ERROR HANDLING IN A GEOMETRIC CORRECTION ENGINE simplified abstract (Texas Instruments Incorporated)|18465250]])=== | | ===ERROR HANDLING IN A GEOMETRIC CORRECTION ENGINE ([[18465250. ERROR HANDLING IN A GEOMETRIC CORRECTION ENGINE simplified abstract (Texas Instruments Incorporated)|18465250]])=== |
| Line 505: |
Line 137: |
| | Gang Hua | | Gang Hua |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a method for error handling in a geometric correction engine (GCE). Here is a simplified explanation of the abstract:
| |
| − |
| |
| − | * The GCE receives configuration parameters that define how it should operate.
| |
| − | * Based on these parameters, the GCE generates output blocks of an output frame by processing corresponding blocks of an input frame.
| |
| − | * During this generation process, the GCE detects any run-time errors that occur.
| |
| − | * When a run-time error is detected, the GCE reports an event that corresponds to the error.
| |
| − |
| |
| − | Potential Applications:
| |
| − |
| |
| − | * Geometric correction engines are commonly used in image and video processing applications, such as in projectors or display systems. This method can be applied in these fields to handle errors during the geometric correction process.
| |
| − |
| |
| − | Problems Solved:
| |
| − |
| |
| − | * Geometric correction engines often encounter errors during the generation of output frames. This method provides a systematic approach to handle these errors and report them, allowing for better error management and troubleshooting.
| |
| − |
| |
| − | Benefits:
| |
| − |
| |
| − | * Improved error handling: The method provides a way to detect and report run-time errors during the generation process, allowing for timely identification and resolution of issues.
| |
| − | * Enhanced reliability: By effectively handling errors, the method helps ensure that the output frames are accurately generated, leading to improved reliability of the geometric correction engine.
| |
| − | * Efficient troubleshooting: The reported events corresponding to errors can assist in troubleshooting and diagnosing issues, making it easier to identify and resolve problems in the GCE.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method for error handling in a geometric correction engine (GCE) is provided that includes receiving configuration parameters by the GCE, generating, by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting, by the GCE, a run-time error during the generating, and reporting, by the GCE, an event corresponding to the run-time error.
| |
| | | | |
| | ===METHOD OF REDUCING VOIDS AND SEAMS IN TRENCH STRUCTURES BY FORMING SEMI-AMORPHOUS POLYSILICON ([[18346977. METHOD OF REDUCING VOIDS AND SEAMS IN TRENCH STRUCTURES BY FORMING SEMI-AMORPHOUS POLYSILICON simplified abstract (Texas Instruments Incorporated)|18346977]])=== | | ===METHOD OF REDUCING VOIDS AND SEAMS IN TRENCH STRUCTURES BY FORMING SEMI-AMORPHOUS POLYSILICON ([[18346977. METHOD OF REDUCING VOIDS AND SEAMS IN TRENCH STRUCTURES BY FORMING SEMI-AMORPHOUS POLYSILICON simplified abstract (Texas Instruments Incorporated)|18346977]])=== |
| Line 538: |
Line 145: |
| | Damien Thomas Gilmore | | Damien Thomas Gilmore |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a microelectronic device that has a trench structure. The device is formed by creating a trench in a substrate and then depositing a seed layer made of amorphous dielectric material in the trench. Semi-amorphous polysilicon is then formed on top of the seed layer, with amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes can convert the semi-amorphous polysilicon into a polysilicon core.
| |
| − |
| |
| − | * The microelectronic device has a trench structure.
| |
| − | * A seed layer made of amorphous dielectric material is deposited in the trench.
| |
| − | * Semi-amorphous polysilicon is formed on top of the seed layer.
| |
| − | * The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon.
| |
| − | * Subsequent thermal processes can convert the semi-amorphous polysilicon into a polysilicon core.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Microelectronic devices with trench structures, such as transistors or capacitors.
| |
| − | * Semiconductor manufacturing processes.
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Provides a method for forming a trench structure in a microelectronic device.
| |
| − | * Allows for the formation of a polysilicon core in the trench through subsequent thermal processes.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Enables the creation of complex microelectronic devices with trench structures.
| |
| − | * Provides a reliable and efficient method for forming the trench structure and the polysilicon core.
| |
| − | * Can be integrated into existing semiconductor manufacturing processes.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE WITH MULTIPLE DIES ([[17850187. SEMICONDUCTOR DEVICE WITH MULTIPLE DIES simplified abstract (Texas Instruments Incorporated)|17850187]])=== | | ===SEMICONDUCTOR DEVICE WITH MULTIPLE DIES ([[17850187. SEMICONDUCTOR DEVICE WITH MULTIPLE DIES simplified abstract (Texas Instruments Incorporated)|17850187]])=== |
| Line 574: |
Line 153: |
| | YIQI TANG | | YIQI TANG |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a semiconductor device that includes a multi-layer package substrate. The substrate has multiple layers patterned to provide pads and vias for connecting ports of two different dies. The substrate also includes traces and a ground plane for coupling the ports of the first die to the ports of the second die.
| |
| − |
| |
| − | * The semiconductor device includes a multi-layer package substrate.
| |
| − | * The substrate has multiple layers patterned to provide pads for the ports of the first and second dies.
| |
| − | * The substrate also has vias that connect the pads for the ports of the first die to the pads for the ports of the second die.
| |
| − | * The substrate includes traces on a third layer that couple the vias connected to the ports of the first die to the vias connected to the ports of the second die.
| |
| − | * The traces on the third layer have a specific width.
| |
| − | * The substrate also includes a fourth layer and a ground plane underlying the fourth layer.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * This technology can be used in various semiconductor devices, such as integrated circuits and microprocessors.
| |
| − | * It can be applied in electronic devices like smartphones, tablets, and computers.
| |
| − | * It can be used in automotive electronics, aerospace systems, and industrial equipment.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * The multi-layer package substrate solves the problem of connecting ports of different dies in a semiconductor device.
| |
| − | * It provides a reliable and efficient way to couple the first die to the second die.
| |
| − | * The use of vias and traces ensures proper signal transmission between the dies.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * The multi-layer package substrate allows for compact and space-efficient designs.
| |
| − | * It provides a high level of integration and connectivity between different dies.
| |
| − | * The technology enables faster and more efficient data transfer between the dies.
| |
| − | * It improves the overall performance and reliability of the semiconductor device.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor device includes a first die having ports and a second die having ports. The semiconductor device includes a multi-layer package substrate. The multi-layer package substrate includes a first layer patterned to include pads for the ports of the first die and the second die and a second layer patterned to provide vias between the pads for the ports of the first die and pads for the ports of the second die and a third layer of the multi-layer package substrate. The third layer is patterned to provide traces that couple the vias coupled to ports of the first die to vias coupled to ports of the second die to couple the first die to the second die, the traces of the third layer having a width. The multi-layer package substrate also includes a fourth layer underlying the third layer and a ground plane underlying the fourth layer.
| |
| | | | |
| | ===STANDALONE HIGH VOLTAGE GALVANIC ISOLATION CAPACITORS ([[18242717. STANDALONE HIGH VOLTAGE GALVANIC ISOLATION CAPACITORS simplified abstract (Texas Instruments Incorporated)|18242717]])=== | | ===STANDALONE HIGH VOLTAGE GALVANIC ISOLATION CAPACITORS ([[18242717. STANDALONE HIGH VOLTAGE GALVANIC ISOLATION CAPACITORS simplified abstract (Texas Instruments Incorporated)|18242717]])=== |
| Line 611: |
Line 161: |
| | Thomas Dyer Bonifield | | Thomas Dyer Bonifield |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a galvanic isolation capacitor device that includes a semiconductor substrate and various layers. The device is designed to have specific thickness ratios and area ratios to optimize its performance. It can be used as part of a multi-chip module.
| |
| − |
| |
| − | * The galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over it.
| |
| − | * The PMD layer has a specific thickness, and there is a lower metal plate over it.
| |
| − | * An ILD layer is on the lower metal plate, with a specific thickness ratio to the PMD layer.
| |
| − | * There are two upper metal plates over the ILD layer, with a specific area ratio between them.
| |
| − | * The device can be used in a multi-chip module.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * Multi-chip modules
| |
| − | * Electronic devices requiring galvanic isolation
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * Provides galvanic isolation in electronic devices
| |
| − | * Optimizes the performance of the galvanic isolation capacitor device
| |
| − |
| |
| − | == Benefits ==
| |
| − | * Improved performance and efficiency
| |
| − | * Enhanced galvanic isolation capabilities
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.
| |
| | | | |
| | ===CONTROLLED TRANSITION TO REGULATION ([[18465195. CONTROLLED TRANSITION TO REGULATION simplified abstract (Texas Instruments Incorporated)|18465195]])=== | | ===CONTROLLED TRANSITION TO REGULATION ([[18465195. CONTROLLED TRANSITION TO REGULATION simplified abstract (Texas Instruments Incorporated)|18465195]])=== |
| Line 643: |
Line 169: |
| | Hakan ONER | | Hakan ONER |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a method for regulating battery current using a regulating circuit, an operational transconductance amplifier, and a current source. The regulating circuit receives a battery feedback parameter and produces a first output current at an output terminal based on the battery feedback parameter and a battery current regulation voltage. The operational transconductance amplifier also produces a first output current at the output terminal based on the battery feedback parameter and a reference voltage.
| |
| − |
| |
| − | * The method involves receiving a battery feedback parameter and using it to regulate battery current.
| |
| − | * An operational transconductance amplifier is used to produce a first output current at the output terminal.
| |
| − | * A current source is used to produce a second current at the output terminal.
| |
| − | * The output currents are based on the battery feedback parameter and either a battery current regulation voltage or a reference voltage.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * Battery management systems
| |
| − | * Electric vehicle charging systems
| |
| − | * Renewable energy systems
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * Efficient regulation of battery current
| |
| − | * Improved battery performance and lifespan
| |
| − | * Enhanced control over charging and discharging processes
| |
| − |
| |
| − | == Benefits ==
| |
| − | * Optimal battery current regulation
| |
| − | * Increased battery efficiency
| |
| − | * Extended battery lifespan
| |
| − | * Enhanced control and monitoring capabilities
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method includes receiving, by a regulating circuit, a battery feedback parameter and producing, by an operational transconductance amplifier, a first output current at an output terminal based on the battery feedback parameter and a battery current regulation voltage. The method also includes producing, by a current source, a second current at the output terminal based on the battery feedback parameter and a reference voltage.
| |
| | | | |
| | ===ADAPTING SPLIT-TRANSISTOR SWITCHING POWER SUPPLY BASED ON CONDITION ([[17809238. ADAPTING SPLIT-TRANSISTOR SWITCHING POWER SUPPLY BASED ON CONDITION simplified abstract (Texas Instruments Incorporated)|17809238]])=== | | ===ADAPTING SPLIT-TRANSISTOR SWITCHING POWER SUPPLY BASED ON CONDITION ([[17809238. ADAPTING SPLIT-TRANSISTOR SWITCHING POWER SUPPLY BASED ON CONDITION simplified abstract (Texas Instruments Incorporated)|17809238]])=== |
| Line 678: |
Line 177: |
| | Robert A. Neidorff | | Robert A. Neidorff |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes techniques for controlling a switching converter, which includes a switching element and a logic circuit. The switching element consists of multiple parallel-coupled transistors. The logic circuit initially provides gate drive signals to some of the transistors based on certain conditions associated with the converter, such as RdsOn (drain-source on-resistance) and temperature. After a delay period, the logic circuit provides gate drive signals to all or a larger number of the transistors.
| |
| − |
| |
| − | * The switching converter includes a switching element with multiple parallel-coupled transistors.
| |
| − | * The logic circuit provides gate drive signals to some transistors initially, based on conditions like RdsOn and temperature.
| |
| − | * After a delay period, the logic circuit provides gate drive signals to all or a larger number of the transistors.
| |
| − | * This adaptive sizing of the switching transistors helps dampen ringing initially and reduce conduction loss later.
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | * Power electronics
| |
| − | * Renewable energy systems
| |
| − | * Electric vehicles
| |
| − | * Industrial automation
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | * Damping ringing in switching converters
| |
| − | * Reducing conduction loss in switching converters
| |
| − |
| |
| − | ==Benefits==
| |
| − | * Improved efficiency in switching converters
| |
| − | * Enhanced performance in power electronics systems
| |
| − | * Better control over power conversion processes
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Techniques for controlling a switching converter. In an example, the converter includes a switching element and a logic circuit. The switching element includes a plurality of parallel-coupled transistors. The logic circuit is configured to initially provide one or more gate drive signals to one or more of the parallel-coupled transistors, respectively, but not to all of the transistors. After a delay period, the logic circuit is further configured to provide a respective gate drive signal to all or an otherwise larger number of the transistors. The initially-provided one or more gate signals is/are based on one or more conditions associated with the converter, such as RdsOn associated with the switching element and/or temperature. In this manner, a switching transistor that is adaptively-sized based on the condition(s) is initially switched to damp ringing, and a larger switching transistor (e.g., all transistors in parallel) is subsequently switched for low conduction loss.
| |
| | | | |
| | ===CLOCK MATCHING TUNE CIRCUIT ([[17849484. CLOCK MATCHING TUNE CIRCUIT simplified abstract (Texas Instruments Incorporated)|17849484]])=== | | ===CLOCK MATCHING TUNE CIRCUIT ([[17849484. CLOCK MATCHING TUNE CIRCUIT simplified abstract (Texas Instruments Incorporated)|17849484]])=== |
| Line 712: |
Line 185: |
| | Gebhard HAUG | | Gebhard HAUG |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a system that includes circuitry on two sides of an isolation barrier, which electrically isolates the two sides.
| |
| − |
| |
| − | * The system includes a trimmed oscillator, a first transmitter, and a first receiver on one side, and a tunable oscillator, a second transmitter, and a second receiver on the other side.
| |
| − | * The first side transmits a training sequence to the second side.
| |
| − | * The second side tunes the tunable oscillator based on the training sequence.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * This technology can be used in communication systems that require isolation between different circuitry.
| |
| − | * It can be applied in wireless communication systems, where the tuning of the oscillator is crucial for optimal performance.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * The system solves the problem of achieving electrical isolation between circuitry on different sides of an isolation barrier.
| |
| − | * It also solves the problem of tuning an oscillator based on a training sequence.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * The system provides a reliable and efficient way to transmit signals across an isolation barrier.
| |
| − | * It allows for accurate tuning of the oscillator, leading to improved performance in communication systems.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | In an example, a system includes circuitry on a first side of an isolation barrier and circuitry on a second side of the isolation barrier, where the isolation barrier is operable to electrically isolate the first side from the second side. The system also includes a trimmed oscillator, a first transmitter, and a first receiver on the first side, the trimmed oscillator coupled to the first transmitter. The system includes a tunable oscillator, a second transmitter, and a second receiver on the second side, the tunable oscillator coupled to the second receiver and the second transmitter. In the system, the first side is configured to transmit a training sequence to the second side, and the second side is configured to tune the tunable oscillator based on the training sequence.
| |
| | | | |
| | ===SEMICONDUCTOR SWITCHES FOR HIGH VOLTAGE OPERATIONS ([[18350874. SEMICONDUCTOR SWITCHES FOR HIGH VOLTAGE OPERATIONS simplified abstract (Texas Instruments Incorporated)|18350874]])=== | | ===SEMICONDUCTOR SWITCHES FOR HIGH VOLTAGE OPERATIONS ([[18350874. SEMICONDUCTOR SWITCHES FOR HIGH VOLTAGE OPERATIONS simplified abstract (Texas Instruments Incorporated)|18350874]])=== |
| Line 742: |
Line 193: |
| | Rohan Sinha | | Rohan Sinha |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a semiconductor switch designed for high voltage operations. It consists of two DE-NMOS FETs, with the first one connected to the input and output nodes and the second one connected to the node. The second FET is controlled by a signal that enables or disables the switch. A voltage source is connected to the node, providing a higher voltage than the input node. A current source supplies current to the voltage source.
| |
| − |
| |
| − | * The semiconductor switch is designed for high voltage operations.
| |
| − | * It includes two DE-NMOS FETs, with the first one connected to the input and output nodes.
| |
| − | * The second FET is connected to the node and controlled by a signal.
| |
| − | * A voltage source is connected to the node, providing a higher voltage than the input node.
| |
| − | * A current source supplies current to the voltage source.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * Power electronics
| |
| − | * High voltage systems
| |
| − | * Electric vehicles
| |
| − | * Renewable energy systems
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * Allows for high voltage operations in a safe operating area
| |
| − | * Enables efficient switching in high voltage applications
| |
| − |
| |
| − | == Benefits ==
| |
| − | * Improved safety in high voltage operations
| |
| − | * Enhanced efficiency in high voltage switching
| |
| − | * Suitable for various applications in power electronics and renewable energy systems
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Semiconductor switches for high voltage operations are described. The semiconductor switch includes a first DE-NMOS FET including a gate coupled to a node of the switch with its source and drain coupled to input and output nodes, respectively. The switch also includes a second DE-NMOS FET with a drain coupled to the node. A gate of the second DE-NMOS FET is configured to receive a signal enabling or disabling the switch. The switch includes a voltage source (e.g., a voltage-controlled voltage source) coupled to the node, which supplies a first voltage at the node. The first voltage is greater than a second voltage at the input node by a predetermined amount such that the first DE-NMOS FET may operate within a safe operating area while supporting high voltage operations. The switch also includes a current source configured to supply current to the voltage source.
| |
| | | | |
| | ===ESTIMATING AND CORRECTING TRANSMITTER LOCAL OSCILLATOR LEAKAGE IN LOOPBACK PATH ([[18308556. ESTIMATING AND CORRECTING TRANSMITTER LOCAL OSCILLATOR LEAKAGE IN LOOPBACK PATH simplified abstract (Texas Instruments Incorporated)|18308556]])=== | | ===ESTIMATING AND CORRECTING TRANSMITTER LOCAL OSCILLATOR LEAKAGE IN LOOPBACK PATH ([[18308556. ESTIMATING AND CORRECTING TRANSMITTER LOCAL OSCILLATOR LEAKAGE IN LOOPBACK PATH simplified abstract (Texas Instruments Incorporated)|18308556]])=== |
| Line 777: |
Line 201: |
| | Sucheth Sureshbabu KUNCHAM | | Sucheth Sureshbabu KUNCHAM |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a system that receives a differential input signal from a quadrature amplitude modulation (QAM) transmitter. The system includes switches that can configure the input signals in both non-inverting and inverting configurations, and a complex mixer that produces an output signal based on these configurations.
| |
| − |
| |
| − | * The system receives a differential input signal from a QAM transmitter.
| |
| − | * The first and second switches are used to couple the input signals to a complex mixer in a non-inverting configuration.
| |
| − | * The third and fourth switches are used to couple the input signals to the complex mixer in an inverting configuration.
| |
| − | * The complex mixer produces an output signal based on the non-inverting and inverting configurations.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * This technology can be used in communication systems that utilize quadrature amplitude modulation (QAM) for transmitting data.
| |
| − | * It can be applied in wireless communication systems, such as Wi-Fi or cellular networks, to improve signal reception and processing.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * The system solves the problem of efficiently processing and decoding differential input signals from a QAM transmitter.
| |
| − | * It addresses the challenge of handling both non-inverting and inverting configurations of the input signals.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * The system provides flexibility in configuring the input signals, allowing for improved signal processing and decoding.
| |
| − | * It enhances the overall performance and reliability of communication systems utilizing QAM modulation.
| |
| − | * The technology can potentially lead to better signal reception and higher data transmission rates.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | In an example, a system includes a receiver configured to receive a differential input signal from a quadrature amplitude modulation (QAM) transmitter at a differential interface that includes a first input and a second input. The system also includes a first switch coupled to the first input and a second switch coupled to the second input, where the first switch and second switch are configured to couple the first input and the second input to a complex mixer in a non-inverting configuration. The system includes a third switch coupled to the first input and a fourth switch coupled to the second input, where the third switch and the fourth switch are configured to couple the first input and the second input to the complex mixer in an inverting configuration. The complex mixer is configured to produce an output signal based on the non-inverting configuration and the inverting configuration.
| |
| | | | |
| | ===DATA ENCODER FOR POWER LINE COMMUNICATIONS ([[18460837. DATA ENCODER FOR POWER LINE COMMUNICATIONS simplified abstract (Texas Instruments Incorporated)|18460837]])=== | | ===DATA ENCODER FOR POWER LINE COMMUNICATIONS ([[18460837. DATA ENCODER FOR POWER LINE COMMUNICATIONS simplified abstract (Texas Instruments Incorporated)|18460837]])=== |
| Line 809: |
Line 209: |
| | Badri N. Varadarajan | | Badri N. Varadarajan |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a power line communication (PLC) transmitter that uses forward error correction (FEC) encoding, fragmenting, fragment repetition encoding, and interleaving techniques to improve data transmission on a power line.
| |
| − |
| |
| − | * The PLC transmitter includes a FEC encoder that adds parity information to payload data to create an encoded output.
| |
| − | * The encoded output is then segmented into multiple fragments by a fragmenter.
| |
| − | * A fragment repetition encoder copies each fragment a selected number of times to increase data reliability.
| |
| − | * The copies of the fragments are interleaved by an interleaver for transmission on a power line.
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | * Power line communication systems
| |
| − | * Smart grid technology
| |
| − | * Home automation systems
| |
| − | * Industrial control systems
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | * Data transmission errors and losses on power lines
| |
| − | * Improving reliability and efficiency of power line communication
| |
| − | * Enhancing the performance of smart grid and automation systems
| |
| − |
| |
| − | ==Benefits==
| |
| − | * Improved data transmission reliability on power lines
| |
| − | * Increased efficiency and performance of power line communication systems
| |
| − | * Enhanced reliability and functionality of smart grid and automation technologies
| |
| − |
| |
| − | '''Abstract'''
| |
| − | In a disclosed embodiment, a power line communication (PLC) transmitter includes a forward error correction (FEC) encoder that receives payload data and adds parity information to the data to create an encoded output, a fragmenter that receives the encoded output from the FEC encoder and segments the encoded output into a plurality of fragments, a fragment repetition encoder that receives the plurality of fragments from the fragmenter and copies each of the fragments a selected number of times, and an interleaver that receives the copies of the plurality of fragments from the fragment repetition encoder and interleaves the copies of the plurality of fragments for transmission on a power line.
| |
| | | | |
| | ===DECOUPLING TRANSMITTER FROM LOOPBACK PATH IQMM WITH PHASE DELAY-ELIMINATION BY ROTATION ([[18338895. DECOUPLING TRANSMITTER FROM LOOPBACK PATH IQMM WITH PHASE DELAY-ELIMINATION BY ROTATION simplified abstract (Texas Instruments Incorporated)|18338895]])=== | | ===DECOUPLING TRANSMITTER FROM LOOPBACK PATH IQMM WITH PHASE DELAY-ELIMINATION BY ROTATION ([[18338895. DECOUPLING TRANSMITTER FROM LOOPBACK PATH IQMM WITH PHASE DELAY-ELIMINATION BY ROTATION simplified abstract (Texas Instruments Incorporated)|18338895]])=== |
| Line 844: |
Line 217: |
| | Prakhar AGRAWAL | | Prakhar AGRAWAL |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a system that includes a transmitter, receiver, delay element, and controller for correcting IQ mismatch in a transmitter-receiver loop.
| |
| − |
| |
| − | * The system transmits a quadrature amplitude modulation (QAM) signal, which consists of an in-phase (I) chain signal and a quadrature (Q) chain signal.
| |
| − | * A delay element is used to introduce a phase delay between the transmitter and the receiver.
| |
| − | * The controller determines the IQ mismatch (IQMM) of the transmitter-receiver loop without a phase delay and with a phase delay introduced by the delay element.
| |
| − | * Based on these IQMM measurements, the controller corrects the IQMM of the transmitter.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * This technology can be applied in wireless communication systems that use QAM modulation.
| |
| − | * It can be used in various wireless devices such as smartphones, tablets, and IoT devices.
| |
| − | * The system can improve the performance and reliability of wireless communication by reducing IQ mismatch.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * IQ mismatch in a transmitter-receiver loop can cause signal distortion and degradation in wireless communication systems.
| |
| − | * This technology solves the problem of IQ mismatch by accurately measuring and correcting it.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * By correcting IQ mismatch, the system improves the quality and accuracy of transmitted signals.
| |
| − | * It enhances the overall performance and efficiency of wireless communication systems.
| |
| − | * The technology can lead to better signal reception, reduced interference, and improved data transmission rates.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | In an example, a system includes a transmitter configured to transmit a quadrature amplitude modulation (QAM) signal, where the QAM signal includes an in-phase (I) chain signal and a quadrature (Q) chain signal. The system includes a receiver configured to receive the QAM signal from the transmitter. The system includes a delay element configured to introduce a phase delay between the transmitter and the receiver. The system includes a controller configured to determine an IQ mismatch (IQMM) of a transmitter-receiver loop without a phase delay, and to determine an IQMM of the transmitter-receiver loop with a phase delay introduced by the delay element. The controller is configured to determine an IQMM of the transmitter based on the IQMM of the transmitter-receiver loop without the phase delay and the IQMM of the transmitter-receiver loop with the phase delay. The controller is configured to correct the IQMM of the transmitter.
| |
| | | | |
| | ===ADVANCED SWITCH NODE SELECTION FOR POWER LINE COMMUNICATIONS NETWORK ([[18465219. ADVANCED SWITCH NODE SELECTION FOR POWER LINE COMMUNICATIONS NETWORK simplified abstract (Texas Instruments Incorporated)|18465219]])=== | | ===ADVANCED SWITCH NODE SELECTION FOR POWER LINE COMMUNICATIONS NETWORK ([[18465219. ADVANCED SWITCH NODE SELECTION FOR POWER LINE COMMUNICATIONS NETWORK simplified abstract (Texas Instruments Incorporated)|18465219]])=== |
| Line 877: |
Line 225: |
| | Ramanuja Vedantham | | Ramanuja Vedantham |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract of the patent application describes an algorithm designed to improve the efficiency of a PLC (Power Line Communication) network by promoting terminal nodes to switch nodes. This algorithm aims to reduce network overhead, collisions, and the number of levels in the network, while ensuring the selection of appropriate switch nodes based on signal-to-noise ratios (SNRs).
| |
| − |
| |
| − | * The algorithm promotes terminal nodes to switch nodes in a PLC network.
| |
| − | * It reduces overall network overhead and collisions.
| |
| − | * The algorithm ensures the appropriate selection of switch nodes based on SNRs.
| |
| − | * It minimizes the number of levels in the PLC network.
| |
| − | * The algorithm favors nodes closer to the DC (Direct Current) to promote them as switch nodes.
| |
| − | * Nodes closer to the DC require a smaller number of PNPDUs (Physical Network Protocol Data Units) compared to nodes farther away from the DC.
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | This technology can be applied in various industries and scenarios where PLC networks are used, such as:
| |
| − |
| |
| − | * Smart grid systems
| |
| − | * Home automation
| |
| − | * Industrial control systems
| |
| − | * Building management systems
| |
| − | * Internet of Things (IoT) applications
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | The algorithm addresses several problems in PLC networks:
| |
| − |
| |
| − | * Network overhead: By promoting terminal nodes to switch nodes, the algorithm reduces the overall network overhead, leading to improved efficiency.
| |
| − | * Collisions: The algorithm helps minimize collisions in the network, enhancing data transmission reliability.
| |
| − | * Number of levels: By minimizing the number of levels in the PLC network, the algorithm simplifies the network structure and reduces complexity.
| |
| − |
| |
| − | ==Benefits==
| |
| − | The algorithm offers several benefits to PLC networks:
| |
| − |
| |
| − | * Improved efficiency: By reducing network overhead and collisions, the algorithm enhances the overall efficiency of the PLC network.
| |
| − | * Optimal node selection: The algorithm ensures the appropriate selection of switch nodes based on SNRs, leading to better network performance.
| |
| − | * Simplified network structure: By minimizing the number of levels in the network, the algorithm simplifies the network structure, making it easier to manage and maintain.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | An algorithm for the promotion of terminal nodes to switch nodes in a PLC network reduces overall network overhead and collisions, while ensuring the appropriate selection of a switch node and minimizing the number of levels in a PLC network. It also ensures that the terminal nodes with appropriate signal-to-noise ratios (SNRs) are promoted. It is desirable to have a network with fewer levels. The disclosed approach favors the nodes that are closer to the DC to promote them as switch nodes. This is achieved by waiting for a smaller number of PNPDUs for a node that is closer to the DC in comparison to a node that is farther away from the DC.
| |
| | | | |
| | ===COMPRESSED CHIP TO CHIP TRANSMISSION ([[18342389. COMPRESSED CHIP TO CHIP TRANSMISSION simplified abstract (Texas Instruments Incorporated)|18342389]])=== | | ===COMPRESSED CHIP TO CHIP TRANSMISSION ([[18342389. COMPRESSED CHIP TO CHIP TRANSMISSION simplified abstract (Texas Instruments Incorporated)|18342389]])=== |
| Line 921: |
Line 233: |
| | Jonathan Andrew LUCAS | | Jonathan Andrew LUCAS |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract of the patent application describes a method that involves serializing image data for a first image into a format other than RGB pixels and then transmitting this serialized data via RGB signaling lines to map it to RGB pixels of a second image.
| |
| − |
| |
| − | * The method involves converting image data from a non-RGB pixel format to serialized data.
| |
| − | * The serialized data is then transmitted using RGB signaling lines.
| |
| − | * The serialized data is mapped to RGB pixels of a second image.
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | This technology could have various applications in fields such as:
| |
| − |
| |
| − | * Image processing and editing software.
| |
| − | * Digital cameras and photography.
| |
| − | * Video game development.
| |
| − | * Virtual reality and augmented reality systems.
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | The technology addresses the following problems:
| |
| − |
| |
| − | * Converting image data from one format to another can be time-consuming and complex.
| |
| − | * Transmitting serialized data efficiently and accurately can be challenging.
| |
| − | * Mapping serialized data to RGB pixels of a different image format can be problematic.
| |
| − |
| |
| − | ==Benefits==
| |
| − | The technology offers several benefits:
| |
| − |
| |
| − | * Simplifies the process of converting image data between different formats.
| |
| − | * Enables efficient transmission of serialized data via RGB signaling lines.
| |
| − | * Facilitates mapping serialized data to RGB pixels of a second image accurately.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | In some examples, a method includes serializing, via a processor, image data for a first image to form serialized data mapped to RBG pixels of a second image, the image data in a format other than a RGB pixel format. The method also includes transmitting, by the processor, the serialized data via RGB signaling lines.
| |
| | | | |
| | ===SUB-PICTURES FOR PIXEL RATE BALANCING ([[18242241. SUB-PICTURES FOR PIXEL RATE BALANCING simplified abstract (Texas Instruments Incorporated)|18242241]])=== | | ===SUB-PICTURES FOR PIXEL RATE BALANCING ([[18242241. SUB-PICTURES FOR PIXEL RATE BALANCING simplified abstract (Texas Instruments Incorporated)|18242241]])=== |
| Line 961: |
Line 241: |
| | Minhua Zhou | | Minhua Zhou |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a method for decoding a compressed video bit stream in a video decoder to recover a video sequence. The method involves determining that a picture is encoded as a pre-determined number of independently encoded sub-pictures and dispatching these sub-pictures to different decoder processing cores for parallel decoding.
| |
| − |
| |
| − | * The method decodes a compressed video bit stream to recover a video sequence.
| |
| − | * It identifies pictures encoded as a pre-determined number of independently encoded sub-pictures.
| |
| − | * The sub-pictures are dispatched to different decoder processing cores for parallel decoding.
| |
| − | * Each sub-picture is independently decoded on its respective decoder processing core.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * Video decoding in multimedia devices such as smartphones, tablets, and smart TVs.
| |
| − | * Video streaming services and platforms.
| |
| − | * Video conferencing and communication applications.
| |
| − | * Video surveillance systems.
| |
| − | * Virtual reality and augmented reality applications.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * Efficient decoding of compressed video bit streams.
| |
| − | * Parallel decoding of independently encoded sub-pictures.
| |
| − | * Optimizing video decoding performance and speed.
| |
| − | * Enabling real-time video processing and playback.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * Faster and more efficient video decoding process.
| |
| − | * Improved video quality and playback experience.
| |
| − | * Reduced latency in video processing and playback.
| |
| − | * Enhanced performance and scalability of video decoding systems.
| |
| − | * Enables real-time video applications and services.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method for decoding a compressed video bit stream in a video decoder to recover a video sequence, the video decoder including a plurality of decoder processing cores is provided. The method includes determining that a picture is encoded in the compressed bit stream as a pre-determined number of independently encoded sub-pictures, and dispatching a first encoded sub-picture of the pre-determined number of sub-pictures to a first decoder processing core of the plurality of decoder processing cores and a second encoded sub-picture of the pre-determined number of sub-pictures to a second decoder processing core of the plurality of decoder processing cores, wherein the first encoded sub-picture and the second encoded sub-picture are independently decoded in parallel on the respective first and second decoder processing cores.
| |
| | | | |
| | ===LINE-BASED COMPRESSION FOR DIGITAL IMAGE DATA ([[18464433. LINE-BASED COMPRESSION FOR DIGITAL IMAGE DATA simplified abstract (Texas Instruments Incorporated)|18464433]])=== | | ===LINE-BASED COMPRESSION FOR DIGITAL IMAGE DATA ([[18464433. LINE-BASED COMPRESSION FOR DIGITAL IMAGE DATA simplified abstract (Texas Instruments Incorporated)|18464433]])=== |
| Line 1,000: |
Line 249: |
| | Ying Chen | | Ying Chen |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a method for compressing digital image data using variable length entropy codes and spatial prediction. The method involves selecting an entropy code from a set of codes, using spatial prediction to calculate a pixel predictor and residual for each pixel in a line of pixels, and encoding the pixel residual using either the selected entropy code or run mode encoding.
| |
| − |
| |
| − | * Method for compressing digital image data using variable length entropy codes and spatial prediction
| |
| − | * Selecting an entropy code from a set of codes
| |
| − | * Using spatial prediction to compute a pixel predictor and residual for each pixel in a line of pixels
| |
| − | * Encoding the pixel residual using either the selected entropy code or run mode encoding
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | * Image compression for storage or transmission purposes
| |
| − | * Efficient encoding of digital images in various applications such as multimedia, telecommunications, and computer vision
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | * Reducing the size of digital image data for efficient storage and transmission
| |
| − | * Improving the compression ratio without significant loss of image quality
| |
| − | * Enhancing the speed and efficiency of image encoding and decoding processes
| |
| − |
| |
| − | ==Benefits==
| |
| − | * Higher compression ratios leading to reduced storage requirements and faster transmission
| |
| − | * Improved image quality preservation during compression and decompression
| |
| − | * Faster encoding and decoding processes for digital images
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method of compressing digital image data is provided that includes selecting an entropy code for encoding a line of pixels in the digital image data, wherein the entropy code is selected from a plurality of variable length entropy codes, using spatial prediction to compute a pixel predictor and a pixel residual for a pixel in the line of pixels, and selectively encoding the pixel residual using one of the entropy code or run mode encoding.
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| | ===BLE CHANNEL AWARE OPERATION PARAMETERS ([[17850784. BLE CHANNEL AWARE OPERATION PARAMETERS simplified abstract (Texas Instruments Incorporated)|17850784]])=== | | ===BLE CHANNEL AWARE OPERATION PARAMETERS ([[17850784. BLE CHANNEL AWARE OPERATION PARAMETERS simplified abstract (Texas Instruments Incorporated)|17850784]])=== |
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| | Yaron ALPERT | | Yaron ALPERT |
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| − | '''Brief explanation'''
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| − | The abstract describes a method for communication between two Bluetooth devices using different channels and specific parameters for each channel. The first device communicates with the second device on the first channel using first channel specific parameters. Then, the first device determines operation parameters for a second channel and communicates with the second device using renegotiated second channel specific parameters.
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| − |
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| − | * The method allows communication between Bluetooth devices using different channels and specific parameters for each channel.
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| − | * The first device communicates with the second device on the first channel using first channel specific parameters.
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| − | * The first device determines operation parameters for a second channel at a later connection event.
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| − | * The first device communicates with the second device on the second channel using renegotiated second channel specific parameters.
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| − |
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| − | == Potential Applications ==
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| − | * Wireless audio streaming between Bluetooth devices.
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| − | * Data transfer between Bluetooth-enabled devices.
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| − | * IoT devices communicating with each other over Bluetooth.
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| − |
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| − | == Problems Solved ==
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| − | * Enables efficient communication between Bluetooth devices using different channels.
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| − | * Facilitates seamless switching between channels during connection events.
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| − | * Provides flexibility in determining and renegotiating channel specific parameters.
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| − |
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| − | == Benefits ==
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| − | * Improved performance and reliability of Bluetooth communication.
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| − | * Enhanced flexibility in channel selection and parameter negotiation.
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| − | * Enables more efficient use of Bluetooth resources.
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| − | * Simplifies the process of establishing and maintaining Bluetooth connections.
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| − |
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| − | '''Abstract'''
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| − | In an example, a method includes communicating between a first BLUETOOTH device and a second BLUETOOTH device via a first channel within a channel set at a first connection event using first channel specific parameters. The method also includes determining, by the first BLUETOOTH device, one or more channel cluster operation parameters for a second channel within the channel set at a second connection event using second channel specific parameters. The method includes communicating over the second channel during the second connection event from the first BLUETOOTH device to the second BLUETOOTH device using renegotiated second channel specific parameters.
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| | ===PHYSICAL DOWNLINK CONTROL CHANNEL AND PHYSICAL HYBRID AUTOMATIC REPEAT REQUEST INDICATOR CHANNEL ENHANCEMENTS ([[18244623. PHYSICAL DOWNLINK CONTROL CHANNEL AND PHYSICAL HYBRID AUTOMATIC REPEAT REQUEST INDICATOR CHANNEL ENHANCEMENTS simplified abstract (Texas Instruments Incorporated)|18244623]])=== | | ===PHYSICAL DOWNLINK CONTROL CHANNEL AND PHYSICAL HYBRID AUTOMATIC REPEAT REQUEST INDICATOR CHANNEL ENHANCEMENTS ([[18244623. PHYSICAL DOWNLINK CONTROL CHANNEL AND PHYSICAL HYBRID AUTOMATIC REPEAT REQUEST INDICATOR CHANNEL ENHANCEMENTS simplified abstract (Texas Instruments Incorporated)|18244623]])=== |
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| | Runhua Chen | | Runhua Chen |
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| − | '''Brief explanation'''
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| − | The abstract describes a wireless transmission system that includes a user equipment and a base station. The base station is responsible for creating a downlink control information block, modulating it, precoding it, and transmitting it to the user equipment. The precoded, modulated downlink control information is transmitted on at least one demodulation reference signal antenna port to the user equipment. The information is mapped to a set of physical resource block pairs in a subframe.
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| − |
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| − | * The system includes a user equipment and a base station.
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| − | * The base station creates a downlink control information block.
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| − | * The downlink control information is modulated and precoded.
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| − | * The precoded, modulated downlink control information is transmitted to the user equipment.
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| − | * The transmission is done on at least one demodulation reference signal antenna port.
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| − | * The information is mapped to a set of physical resource block pairs in a subframe.
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| − |
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| − | == Potential Applications ==
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| − | * Wireless communication systems
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| − | * Mobile networks
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| − | * Internet of Things (IoT) devices
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| − |
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| − | == Problems Solved ==
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| − | * Efficient transmission of downlink control information
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| − | * Precoding and modulation of the information for better signal quality
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| − | * Mapping the information to physical resource block pairs for effective transmission
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| − |
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| − | == Benefits ==
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| − | * Improved wireless communication performance
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| − | * Enhanced signal quality for user equipment
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| − | * Efficient utilization of resources
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| − |
| |
| − | '''Abstract'''
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| − | A wireless transmission system included at least one user equipment and a base station. The base station is operable to form a downlink control information block, modulate the downlink control information, precode the modulated downlink control information, and transmit the precoded, modulated downlink control information on at least one demodulation reference signal antenna port to the at least one user equipment. The precoded, modulated downlink control information is mapped to a set of N1 physical resource block pairs in a subframe from an orthogonal frequency division multiplexing symbol T1 to and orthogonal frequency division multiplexing symbol T2.
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| | ===RATE AND ANTENNA SELECTION USING SINGLE TXOP ([[17850715. RATE AND ANTENNA SELECTION USING SINGLE TXOP simplified abstract (Texas Instruments Incorporated)|17850715]])=== | | ===RATE AND ANTENNA SELECTION USING SINGLE TXOP ([[17850715. RATE AND ANTENNA SELECTION USING SINGLE TXOP simplified abstract (Texas Instruments Incorporated)|17850715]])=== |
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| | Yuval MATAR | | Yuval MATAR |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract describes a method for improving Wi-Fi communication by using multiple antennas and feedback. Here are the key points:
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| − |
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| − | * The method involves a probing Wi-Fi device obtaining a transmit opportunity (TXOP) on a Wi-Fi channel.
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| − | * The probing Wi-Fi device then transmits a probe packet to a receiving Wi-Fi device using a first antenna during the TXOP.
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| − | * First feedback is received in response to transmitting the probe packet with the first antenna.
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| − | * The probe packet is then transmitted again from the probing Wi-Fi device to the receiving Wi-Fi device, but this time using a second antenna during the TXOP.
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| − | * Second feedback is received in response to transmitting the probe packet with the second antenna.
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| − | * Based on the feedback received, the probing Wi-Fi device sets the transmission parameters and selects the antenna to use.
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| − |
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| − | Potential applications of this technology:
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| − |
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| − | * Improving Wi-Fi performance and reliability in various environments, such as homes, offices, public spaces, and industrial settings.
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| − | * Enhancing wireless communication in IoT (Internet of Things) devices, allowing for more efficient data transmission and connectivity.
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| − |
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| − | Problems solved by this technology:
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| − |
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| − | * Overcoming limitations of single-antenna Wi-Fi devices, such as signal interference, weak reception, and limited coverage.
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| − | * Addressing the need for adaptive transmission parameters and antenna selection to optimize Wi-Fi communication in dynamic environments.
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| − |
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| − | Benefits of this technology:
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| − |
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| − | * Improved Wi-Fi signal strength, range, and overall performance.
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| − | * Enhanced reliability and stability of wireless connections.
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| − | * Increased data transfer rates and reduced latency.
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| − | * Better adaptability to changing Wi-Fi conditions and interference.
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| − |
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| − | '''Abstract'''
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| − | In an example, a method includes obtaining, in a probing Wi-Fi device a transmit opportunity (TXOP) on a Wi-Fi channel. The method also includes transmitting a probe packet from the probing Wi-Fi device to a receiving Wi-Fi device during the TXOP with a first antenna. The method includes receiving first feedback responsive to transmitting the probe packet with the first antenna. The method also includes transmitting the probe packet from the probing Wi-Fi device to the receiving Wi-Fi device during the TXOP with a second antenna. The method includes receiving second feedback responsive to transmitting the probe packet with the second antenna. The method also includes setting, by the probing Wi-Fi device, a transmission parameters set and a selected antenna based at least in part on the first feedback or the second feedback.
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