18242717. STANDALONE HIGH VOLTAGE GALVANIC ISOLATION CAPACITORS simplified abstract (Texas Instruments Incorporated)
STANDALONE HIGH VOLTAGE GALVANIC ISOLATION CAPACITORS
Organization Name
Texas Instruments Incorporated
Inventor(s)
Thomas Dyer Bonifield of Dallas TX (US)
Jeffrey Alan West of Dallas TX (US)
Byron Lovell Williams of Plano TX (US)
Elizabeth Costner Stewart of Dallas TX (US)
STANDALONE HIGH VOLTAGE GALVANIC ISOLATION CAPACITORS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18242717 titled 'STANDALONE HIGH VOLTAGE GALVANIC ISOLATION CAPACITORS
Simplified Explanation
The abstract describes a galvanic isolation capacitor device that includes a semiconductor substrate and various layers. The device is designed to have specific thickness ratios and area ratios to optimize its performance. It can be used as part of a multi-chip module.
- The galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over it.
- The PMD layer has a specific thickness, and there is a lower metal plate over it.
- An ILD layer is on the lower metal plate, with a specific thickness ratio to the PMD layer.
- There are two upper metal plates over the ILD layer, with a specific area ratio between them.
- The device can be used in a multi-chip module.
Potential Applications
- Multi-chip modules
- Electronic devices requiring galvanic isolation
Problems Solved
- Provides galvanic isolation in electronic devices
- Optimizes the performance of the galvanic isolation capacitor device
Benefits
- Improved performance and efficiency
- Enhanced galvanic isolation capabilities
Original Abstract Submitted
A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.
