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Category:Tao Chu of Portland OR (US)
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Pages in category "Tao Chu of Portland OR (US)"
The following 7 pages are in this category, out of 7 total.
1
- 17940194. EPITAXIAL REGIONS EXTENDING BETWEEN INNER GATE SPACERS simplified abstract (Intel Corporation)
- 17940195. BARRIER LAYER FOR DIELECTRIC RECESS MITIGATION simplified abstract (Intel Corporation)
- 17940944. FIN TRIM PLUG STRUCTURES WITH METAL FOR IMPARTING CHANNEL STRESS simplified abstract (Intel Corporation)
- 17956188. ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT simplified abstract (Intel Corporation)
I
- Intel corporation (20240105718). INTEGRATED CIRCUIT DEVICES WITH PROTECTION LINER BETWEEN DOPED SEMICONDUCTOR REGIONS simplified abstract
- Intel corporation (20240105770). NECKED RIBBON FOR BETTER N WORKFUNCTION FILLING AND DEVICE PERFORMANCE simplified abstract
- Intel corporation (20240113118). ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT simplified abstract