17956188. ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT simplified abstract (Intel Corporation)

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ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT

Organization Name

Intel Corporation

Inventor(s)

Tao Chu of Portland OR (US)

Minwoo Jang of Portland OR (US)

Yanbin Luo of Portland OR (US)

Paul A. Packan of Hillsboro OR (US)

ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT - A simplified explanation of the abstract

This abstract first appeared for US patent application 17956188 titled 'ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT

Simplified Explanation

The patent application describes integrated circuit dies, apparatuses, systems, and techniques related to low and ultra-low threshold voltage transistor cells.

  • Separate semiconductor bodies are contacted by separate gate electrodes with a dielectric material in between in the first transistor cell.
  • The second transistor cell has separate semiconductor bodies contacted by a shared gate electrode that couples to both bodies.
  • Transistors in the second cell can operate at a lower threshold voltage due to increased strain on the semiconductor bodies from the shared gate electrode.

Potential Applications

This technology could be applied in:

  • High-performance computing
  • Mobile devices
  • Internet of Things (IoT) devices

Problems Solved

  • Lowering threshold voltage for improved performance
  • Increasing strain on semiconductor bodies for enhanced efficiency

Benefits

  • Improved transistor performance
  • Enhanced energy efficiency
  • Increased speed and reliability of electronic devices

Potential Commercial Applications

"Low and Ultra-Low Threshold Voltage Transistor Cells: Commercial Applications"

Possible Prior Art

No prior art is known at this time.

Unanswered Questions

How does this technology impact power consumption in electronic devices?

This technology could potentially reduce power consumption in electronic devices by allowing for lower threshold voltages, but the exact impact would depend on the specific implementation and usage of the technology.

What are the potential challenges in scaling this technology for mass production?

Scaling this technology for mass production may face challenges related to manufacturing processes, cost-effectiveness, and ensuring consistent performance across a large number of devices. Additional research and development may be needed to address these challenges.


Original Abstract Submitted

Integrated circuit dies, apparatuses, systems, and techniques, are described herein related to low and ultra-low threshold voltage transistor cells. A first transistor cell includes separate semiconductor bodies contacted by separate gate electrodes having a dielectric material therebetween. A second transistor cell includes separate semiconductor bodies contacted by a shared gate electrode that couples to both semiconductor bodies. Transistors of the second transistor cell may be operated at a lower threshold voltage than those of the first transistor cell due to increased strain on the semiconductor bodies from the shared gate electrode.