Category:Mustafa N. Kaynak of San Diego CA (US)
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Mustafa N. Kaynak of San Diego CA (US)
Executive Summary
Mustafa N. Kaynak of San Diego CA (US) is an inventor who has filed 19 patents. Their primary areas of innovation include {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} (6 patents), {in sector programmable memories, e.g. flash disk ( (6 patents), {in relation to data integrity, e.g. data losses, bit errors} (4 patents), and they have worked with companies such as Micron Technology, Inc. (14 patents), MICRON TECHNOLOGY, INC. (5 patents). Their most frequent collaborators include (18 collaborations), (6 collaborations), (4 collaborations).
Patent Filing Activity
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Technology Areas
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List of Technology Areas
- G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 6 patents
- G06F11/1068 ({in sector programmable memories, e.g. flash disk (): 6 patents
- G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}): 4 patents
- H03M13/1108 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 4 patents
- G06F3/0604 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 3 patents
- G06F3/0655 ({Replication mechanisms}): 3 patents
- G06F11/076 (Responding to the occurrence of a fault, e.g. fault tolerance): 3 patents
- G06F3/064 ({Management of blocks}): 3 patents
- G11C16/08 (Address circuits; Decoders; Word-line control circuits): 3 patents
- G11C16/26 (Sensing or reading circuits; Data output circuits): 3 patents
- G06F11/1435 ({using file system or storage system metadata}): 2 patents
- G06F3/0673 ({Single storage device}): 2 patents
- G06F3/0629 ({Configuration or reconfiguration of storage systems}): 2 patents
- G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 2 patents
- G06F11/0772 (Responding to the occurrence of a fault, e.g. fault tolerance): 2 patents
- G11C16/3459 ({Circuits or methods to verify correct programming of nonvolatile memory cells}): 2 patents
- G11C16/0483 ({comprising cells having several storage transistors connected in series}): 2 patents
- H03M13/1128 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 2 patents
- G06F3/0653 ({Monitoring storage devices or systems}): 1 patents
- G06F3/0647 ({Migration mechanisms}): 1 patents
- G06F11/1402 ({Saving, restoring, recovering or retrying}): 1 patents
- G11C29/52 (STATIC STORES (semiconductor memory devices): 1 patents
- G06F3/0623 ({in relation to content}): 1 patents
- G06F9/30029 ({Logical and Boolean instructions, e.g. XOR, NOT}): 1 patents
- G06F3/0625 ({Power saving in storage systems}): 1 patents
- G11C7/04 (with means for avoiding disturbances due to temperature effects): 1 patents
- G06F11/0793 ({Remedial or corrective actions (recovery from an exception in an instruction pipeline): 1 patents
- G11C16/10 (Programming or data input circuits): 1 patents
- G11C16/102 (Programming or data input circuits): 1 patents
- H03M13/611 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
- H03M13/098 (Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit): 1 patents
- H03M13/015 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
- G06F12/10 (Address translation): 1 patents
- H03M13/2906 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
- H03M13/3746 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
Companies
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List of Companies
- Micron Technology, Inc.: 14 patents
- MICRON TECHNOLOGY, INC.: 5 patents
Collaborators
- Sivagnanam Parthasarathy of Carlsbad CA (US) (18 collaborations)
- Kishore Kumar Muchherla of San Jose CA (US) (6 collaborations)
- James Fitzpatrick of Laguna Niguel CA (US) (4 collaborations)
- Patrick R. Khayat of San Diego CA (US) (4 collaborations)
- Peter Feeley of Boise ID (US) (3 collaborations)
- Shane Nowell of Boise ID (US) (3 collaborations)
- Mark A. Helm of Santa Cruz CA (US) (3 collaborations)
- Vamsi Pavan Rayaprolu of Santa Clara CA (US) (3 collaborations)
- Steven Michael Kientz of Westminster CO (US) (3 collaborations)
- Kishore Kumar Muchherla of Fremont CA (US) (3 collaborations)
- Ugo Russo of Boise ID (US) (2 collaborations)
- Vamsi Pavan Rayaprolu of San Jose CA (US) (2 collaborations)
- Akira Goda (2 collaborations)
- Eyal En Gad of Highland CA (US) (2 collaborations)
- Devin M. Batutis of San Jose CA (US) (1 collaborations)
- Xiangang Luo of Fremont CA (US) (1 collaborations)
- Sampath Ratnam of Boise ID (US) (1 collaborations)
- Niccolo’ Righetti of Boise ID (US) (1 collaborations)
- Sampath K. Ratnam of San Jose CA (US) (1 collaborations)
- Qisong Lin of El Dorado Hills CA (US) (1 collaborations)
- Patrick Robert Khayat of San Diego CA (US) (1 collaborations)
- Huai-Yuan Tseng of San Ramon CA (US) (1 collaborations)
- Jonathan Scott Parry of Boise ID (US) (1 collaborations)
- Patrick Khayat of San Diego CA (US) (1 collaborations)
- Sampath Ratnam of San Jose CA (US) (1 collaborations)
- Jiangang Wu of Milpitas CA (US) (1 collaborations)
- Jonathan S. Parry of Boise ID (US) (1 collaborations)
- Niccolo' Righetti of Boise ID (US) (1 collaborations)
- Michael Sheperek of Longmont CO (US) (1 collaborations)
- Bruce A. Liikanen of Berthoud CO (US) (1 collaborations)
- Larry J. Koudele of Erie CO (US) (1 collaborations)
Subcategories
This category has the following 4 subcategories, out of 4 total.
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Pages in category "Mustafa N. Kaynak of San Diego CA (US)"
The following 31 pages are in this category, out of 31 total.
1
- 17829913. EARLY STOPPING OF BIT-FLIP LOW DENSITY PARITY CHECK DECODING BASED ON SYNDROME WEIGHT simplified abstract (Micron Technology, Inc.)
- 17829924. SCALED BIT FLIP THRESHOLDS ACROSS COLUMNS FOR IRREGULAR LOW DENSITY PARITY CHECK DECODING simplified abstract (Micron Technology, Inc.)
- 17859468. MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 17860690. MANAGING COMPENSATION FOR CHARGE COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 17860701. MANAGING ERROR COMPENSATION USING CHARGE COUPLING AND LATERAL MIGRATION SENSITIVITY simplified abstract (Micron Technology, Inc.)
- 17860711. MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 17884107. MANAGING COMPENSATION FOR CELL-TO-CELL COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES USING SEGMENTATION simplified abstract (Micron Technology, Inc.)
- 17884113. MANAGING COMPENSATION FOR CELL-TO-CELL COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES BASED ON A SENSITIVITY METRIC simplified abstract (Micron Technology, Inc.)
- 17884432. MULTI-LAYER CODE RATE ARCHITECTURE FOR SPECIAL EVENT PROTECTION WITH REDUCED PERFORMANCE PENALTY simplified abstract (Micron Technology, Inc.)
- 17897869. ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC simplified abstract (Micron Technology, Inc.)
- 18419846. DESCRAMBLING OF SCRAMBLED LINEAR CODEWORDS USING NON-LINEAR SCRAMBLERS simplified abstract (Micron Technology, Inc.)
- 18432326. MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 18511698. MULTI-LAYER CODE RATE ARCHITECTURE FOR COPYBACK BETWEEN PARTITIONS WITH DIFFERENT CODE RATES simplified abstract (Micron Technology, Inc.)
- 18521574. BIT FLIPPING DECODER WITH OPTIMIZED MAXIMUM ITERATIONS FOR VARIED BIT FLIPPING THRESHOLDS simplified abstract (Micron Technology, Inc.)
- 18526634. BLOCK FAMILY-BASED ERROR AVOIDANCE FOR MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 18611450. ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC simplified abstract (Micron Technology, Inc.)
- 18616006. VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE VOLTAGE simplified abstract (Micron Technology, Inc.)
- 18743629. Separation of Parity Columns in Bit-Flip Decoding of Low-Density Parity-Check Codes with Pipelining and Column Parallelism simplified abstract (Micron Technology, Inc.)
- 18753717. MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
- 18821886. Reduction of Errors in Data Retrieved from a Memory Device to Apply an Error Correction Code of a Predetermined Code Rate (Micron Technology, Inc.)
M
- Micron technology, inc. (20240160363). DESCRAMBLING OF SCRAMBLED LINEAR CODEWORDS USING NON-LINEAR SCRAMBLERS simplified abstract
- Micron technology, inc. (20240176509). BIT FLIPPING DECODER WITH OPTIMIZED MAXIMUM ITERATIONS FOR VARIED BIT FLIPPING THRESHOLDS simplified abstract
- Micron technology, inc. (20240176698). MEMORY COMPACTION MANAGEMENT IN MEMORY DEVICES simplified abstract
- Micron technology, inc. (20240231676). VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE VOLTAGE simplified abstract
- Micron technology, inc. (20240232013). ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC simplified abstract
- Micron technology, inc. (20240256328). PREVENTING BACK-TO-BACK FLIPS OF A BIT IN BIT FLIPPING DECODING simplified abstract
- Micron technology, inc. (20240338146). Separation of Parity Columns in Bit-Flip Decoding of Low-Density Parity-Check Codes with Pipelining and Column Parallelism simplified abstract
- Micron technology, inc. (20240347119). MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES simplified abstract
- Micron technology, inc. (20240411459). CODE RATE AS FUNCTION OF LOGICAL SATURATION
- Micron technology, inc. (20240419544). Reduction of Errors in Data Retrieved from a Memory Device to Apply an Error Correction Code of a Predetermined Code Rate
Categories:
- Sivagnanam Parthasarathy of Carlsbad CA (US)
- Kishore Kumar Muchherla of San Jose CA (US)
- James Fitzpatrick of Laguna Niguel CA (US)
- Patrick R. Khayat of San Diego CA (US)
- Peter Feeley of Boise ID (US)
- Shane Nowell of Boise ID (US)
- Mark A. Helm of Santa Cruz CA (US)
- Vamsi Pavan Rayaprolu of Santa Clara CA (US)
- Steven Michael Kientz of Westminster CO (US)
- Kishore Kumar Muchherla of Fremont CA (US)
- Ugo Russo of Boise ID (US)
- Vamsi Pavan Rayaprolu of San Jose CA (US)
- Akira Goda
- Eyal En Gad of Highland CA (US)
- Devin M. Batutis of San Jose CA (US)
- Xiangang Luo of Fremont CA (US)
- Sampath Ratnam of Boise ID (US)
- Niccolo’ Righetti of Boise ID (US)
- Sampath K. Ratnam of San Jose CA (US)
- Qisong Lin of El Dorado Hills CA (US)
- Patrick Robert Khayat of San Diego CA (US)
- Huai-Yuan Tseng of San Ramon CA (US)
- Jonathan Scott Parry of Boise ID (US)
- Patrick Khayat of San Diego CA (US)
- Sampath Ratnam of San Jose CA (US)
- Jiangang Wu of Milpitas CA (US)
- Jonathan S. Parry of Boise ID (US)
- Niccolo' Righetti of Boise ID (US)
- Michael Sheperek of Longmont CO (US)
- Bruce A. Liikanen of Berthoud CO (US)
- Larry J. Koudele of Erie CO (US)
- Mustafa N. Kaynak of San Diego CA (US)
- Inventors
- Inventors filing patents with MICRON TECHNOLOGY, INC.
- Inventors filing patents with Micron Technology, Inc.
