17829924. SCALED BIT FLIP THRESHOLDS ACROSS COLUMNS FOR IRREGULAR LOW DENSITY PARITY CHECK DECODING simplified abstract (Micron Technology, Inc.)
Contents
SCALED BIT FLIP THRESHOLDS ACROSS COLUMNS FOR IRREGULAR LOW DENSITY PARITY CHECK DECODING
Organization Name
Inventor(s)
Eyal En Gad of Santa Clara CA (US)
Mustafa N. Kaynak of San Diego CA (US)
Sivagnanam Parthasarathy of Carlsbad CA (US)
SCALED BIT FLIP THRESHOLDS ACROSS COLUMNS FOR IRREGULAR LOW DENSITY PARITY CHECK DECODING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17829924 titled 'SCALED BIT FLIP THRESHOLDS ACROSS COLUMNS FOR IRREGULAR LOW DENSITY PARITY CHECK DECODING
Simplified Explanation
Abstract: A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.
Explanation:
- A processing device in a memory system reads a sense word from a memory device.
- The processing device executes multiple parity check equations on subsets of the sense word.
- The results of the parity check equations are used to determine a syndrome for the sense word.
- The processing device checks if the syndrome satisfies a codeword criterion.
- If the syndrome does not satisfy the codeword criterion, the processing device performs an iterative LDPC correction process.
- The LDPC correction process uses a scaled bit flip threshold to correct errors in the sense word.
Potential Applications:
- Error correction in memory systems
- Data storage systems
- Communication systems
Problems Solved:
- Correcting errors in memory systems
- Improving data reliability in storage and communication systems
Benefits:
- Improved error correction capabilities
- Enhanced data integrity and reliability
- Increased system performance and efficiency
Original Abstract Submitted
A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.
