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20250218998. Low Temperature Solder Inter (Intel)

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Revision as of 19:52, 3 July 2025 by Wikipatents (talk | contribs) (Automated patent report)
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LOW TEMPERATURE SOLDER INTERCONNECT FOR PACKAGE PITCH SCALING

Abstract: embodiments disclosed herein include an apparatus that comprises a first substrate and a second substrate over the first substrate. in an embodiment, an array of interconnects is provided between the first substrate and the second substrate. the array of interconnects comprises a first interconnect with a first material composition, and a second interconnect with a second material composition that is different than the first material composition.

Inventor(s): Bohan SHAN, Shripad GOKHALE, Rui ZHANG, Mine KAYA, Haobo CHEN, Steve S. CHO, Timothy GOSSELIN, Kartik SRINIVASAN, Edvin CETEGEN, Kyle ARRINGTON, Nicholas S. HAEHN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Ashay DANI, Yoshihiro TOMITA, Ziyin LIN, Yiqun BAI, Jose WAIMIN, Dingying David XU, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Jung Kyu HAN, Liang HE

CPC Classification: H01L24/14 ({of a plurality of bump connectors})

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