Micron technology, inc. (20250118693). TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITECTURES

TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITECTURES

Organization Name

micron technology, inc.

Inventor(s)

Bharat Bhushan of Boise ID US

Kunal R. Parekh of Boise ID US

Akshay N. Singh of Boise ID US

TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITECTURES

This abstract first appeared for US patent application 20250118693 titled 'TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITECTURES

Original Abstract Submitted

methods, systems, and devices for techniques for semiconductor die coupling in stacked memory architectures are described. a semiconductor system may include a semiconductor unit formed by multiple semiconductor dies, where each semiconductor die may be fabricated to be individually separable. each semiconductor die may include a respective portion of circuitry associated with the semiconductor unit. the multiple semiconductor dies may be coupled with a carrier, and each semiconductor die may be coupled (e.g., electrically, communicatively) with at least one other semiconductor die. at least some of the semiconductor dies may be coupled with a respective set of one or more memory arrays, where each memory array may be operable based on the coupling between the multiple semiconductor dies.