Qualcomm incorporated (20250096075). MEMORY CELL STRUCTURES USING FULL BACKSIDE CONNECTIVITY
MEMORY CELL STRUCTURES USING FULL BACKSIDE CONNECTIVITY
Organization Name
Inventor(s)
Shreesh Narasimha of Charlotte NC US
Yandong Gao of San Diego CA US
Peijie Feng of San Diego CA US
MEMORY CELL STRUCTURES USING FULL BACKSIDE CONNECTIVITY
This abstract first appeared for US patent application 20250096075 titled 'MEMORY CELL STRUCTURES USING FULL BACKSIDE CONNECTIVITY
Original Abstract Submitted
in an aspect, a semiconductor memory cell comprises gate structures separated by source or drain (s/d) structures, a frontside (fs) inter-layer dielectric (fs-ild) layer above the gate and s/d structures, fs metal zero (fm0) interconnects above the fs-ild layer, a backside (bs) inter-layer dielectric (bs-ild) layer below the gate and s/d structures, bs metal zero (bm0) interconnects below the bs-ild layer, at least one fs source drain contact (fsdc) electrically connecting an fm0 interconnect to a top surface of an s/d structure, and at least one bs s/d contact (bsdc) electrically connecting a bmo interconnect to a bottom surface of an s/d structure. the semiconductor memory cell comprises nfets and pfets to form a cross-coupled inverter pair. for each inverter in the pair, one of vdd and vss are provided by an fsdc and the other of vdd and vss is provided by a bsdc.