Intel corporation (20250061535). DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

Organization Name

intel corporation

Inventor(s)

Naveen Matam of Rancho Cordova CA (US)

Lance Cheney of El Dorado Hills CA (US)

Eric Finley of Ione CA (US)

Varghese George of Folsom CA (US)

Sanjeev Jahagirdar of Folsom CA (US)

Altug Koker of El Dorado Hills CA (US)

Josh Mastronarde of Sacramento CA (US)

Iqbal Rajwani of Roseville CA (US)

Lakshminarayanan Striramassarma of Folsom CA (US)

Melaku Teshome of El Dorado Hills CA (US)

Vikranth Vemulapalli of Folsom CA (US)

Binoj Xavier of Folsom CA (US)

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

This abstract first appeared for US patent application 20250061535 titled 'DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

Original Abstract Submitted

embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. in one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. a chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. a diverse set of chiplets with different ip core logic can be assembled into a single device.