Patent Applications by Intel Corporation on 18th September 2025

Intel Corporation: 61 patent applications

Intel Corporation has applied for patents in the areas of G06T1/20 (Processor architectures; Processor configuration, e.g. pipelining, 14), G06T1/60 (Memory management, 7), G06F17/16 (Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition, 4), G06F9/30036 ({Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}, 4), H10D30/6735 (Technology classification, 4), G06F13/28 (using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (, 3), H01L23/5283 ({Geometry or} layout of the interconnection structure {(, 3), H10D30/43 (Technology classification, 3), H10D30/6757 (Technology classification, 3), H10D62/121 (Technology classification, 3)

Top Inventors:

Fangwen Fu of Folsom CA US (7 patents)
Julien Carreno of Glounthaune IE (6 patents)
Hong Jiang of Los Altos CA US (5 patents)
Abhishek A. Sharma of Portland OR US (5 patents)
Alexander Heinecke of San Jose CA US (4 patents)
Vasanth Ranganathan of El Dorado Hills CA US (4 patents)
Yongsheng Liu of San Diego CA US (4 patents)
John A. Wiegert of Aloha OR US (4 patents)
Changliang Wang of Bellevue WA US (4 patents)
Altug Koker of El Dorado Hills CA US (4 patents)

Patent Applications by Intel Corporation

20250291126. OPTICAL CONNECTORS WITH INTEGRATED OPTICAL ISOLATORS

Abstract: Disclosed herein are optical connectors for connecting optical components, along with devices related to optical connectors. An example optical connector includes a body with a first connector interface, a second connector interface opposite the first connector interface, and a surface between the f...

20250291127. OPTICAL INTERCONNECTS AND RELATED METHODS

Abstract: Optical interconnects and related methods are disclosed. An example apparatus described herein includes an optical component carrier including a first tapered surface, a second tapered surface, and an optical component, a waveguide carrier including a third tapered surface engaged with the first tap...

20250291134. OPTICAL CONNECTORS WITH ALIGNMENT FEATURES

Abstract: An optical connector includes a body with a first connector interface and a second connector interface opposite the first connector interface. The body includes a first alignment structure and a second alignment structure, and the first and second alignment structure extend between the first connect...

20250291135. OPTICAL INTERCONNECTS AND RELATED METHODS

Abstract: Optical interconnections and related methods are disclosed herein. An optical interconnect disclosed herein includes an optical component carrier including first grooves, the optical component carrier including an optical component including a first end, and a waveguide carrier including second groo...

20250291431. MULTI-FUNCTION STYLUS WITH SENSOR CONTROLLER

Abstract: A system and method for transmitting an input value to a computing device are included herein. The method includes detecting sensor data in a stylus. The method also includes detecting a gesture event with the stylus. In addition, the method includes generating an input value based on the sensor dat...

20250291547. FULLY CONFIGURABLE FLOATING-POINT FORMAT

Abstract: One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. At least one of the plurality of chiplets comprising a graphics processing cluster including a plurality of processin...

20250291550. HARDWARE ACCELERATED RANDOM NUMBER GENERATION

Abstract: One embodiment provides a graphics processor comprising a memory interface and a processing resource coupled with the memory interface. The processing resource includes multiple processing lanes, each of the multiple processing lanes including circuitry dedicated to generation of one or more randomi...

20250291590. GPU ASYNCHRONOUS MATRIX MULTIPLY ACCUMULATE APPLICATIONS

Abstract: One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. At least one of the plurality of chiplets including a plurality of processing elements, a distributed shared local me...

20250291592. ASCON-BASED PROTECTIONS FOR HIGH BANDWIDTH INTERCONNECTS

Abstract: An apparatus to facilitate Ascon-based protections for high bandwidth interconnects is disclosed. The apparatus includes Ascon hardware circuitry of a chiplet hosting processing cores, comprising: an input multiplexer to receive input data for the Ascon hardware circuitry; a first pipeline stage har...

20250291599. FAST PATH CPU MODE FOR MIXED XPU WORKLOADS

Abstract: One embodiment provides a processor device comprising a general-purpose processor including circuitry to provide an offload mode to execute an offloaded instruction and an accelerator device configured to execute a first portion of a data parallel workload, at least a second portion of the data para...

20250291620. ADAPTIVE VIRTUALIZATION OF GPU CORES AND ENGINE BASED VIRTUALIZATION

Abstract: One embodiment provides a graphics processor comprising a memory interface, a plurality of interfaces to a plurality of compute engines, a processing resource cluster including a plurality of processing resources, the plurality of processing resources configured to execute instructions on behalf of ...

20250291633. HARDWARE RESOURCE SERVICE I/O

Abstract: A device includes memory-based cross-domain solutions (M-CDS) circuitry including shared memory and logic to determine that a hardware resource of a first device is to be accessed and used by a program executed on a second device. The logic is to create a buffer in the shared memory region to implem...

20250291680. HARDWARE ASSISTED CHECKPOINT TO ENABLE RECOVERY FROM HARDWARE FAILURES

Abstract: Described herein is a technique to enable hardware driven checkpointing within an accelerator device without requiring explicit host software intervention to generate the checkpoint. One embodiment provides an accelerator device comprising a memory interconnect, a plurality of accelerator cores, and...

20250291723. SIDE-CHANNEL RESISTANT SHARED GPU CACHING WHILE USING PHYSICAL ADDRESSING

Abstract: One embodiment provides a graphics processor comprising a memory interface, a processing resource cluster including a plurality of processing resources, and a cache coupled with the memory interface and the processing resource cluster. The cache includes side-channel resistance circuitry to configur...

20250291731. CROSS-DIE MULTI-CASTING FROM HIGH BANDWIDTH MEMORY IN A GRAPHICS PROCESSING ENVIRONMENT

Abstract: An apparatus to facilitate cross-die multi-casting from high-bandwidth memory in a graphics processing environment is disclosed. The apparatus includes a first processing die comprising: an array of processing cores each comprising processing resources, shared local memory (SLM), and a local direct ...

20250291739. CRYPTO-AGILE FIRMWARE UPDATE

Abstract: Examples described herein relate to updating a cryptographic process. In some examples, circuitry is to update a cryptographic process by a write of a firmware image to a non-volatile memory; authenticate the firmware image based on a hash value stored in One Time Programmable Memory (OTPM); and per...

20250291744. EFFICIENT DATA SHARING FOR GRAPHICS DATA PROCESSING OPERATIONS

Abstract: An apparatus to facilitate efficient data sharing for graphics data processing operations is disclosed. The apparatus includes a processing resource to generate a stream of instructions, an L1 cache communicably coupled to the processing resource and comprising an on-page detector circuit to determi...

20250291746. Tensor Memory Accelerator Enhancements

Abstract: One embodiment provides a graphics processor comprising a memory interface and a graphics core cluster including a plurality of graphics cores and tensor processing circuitry. The tensor processing circuitry includes a local memory, a tensor accelerator coupled with the local memory, the tensor acce...

20250291755. GPU Asynchronous Direct Memory Access Applications

Abstract: One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. A chiplet of the plurality of chiplets including a graphics core cluster including a plurality of graphics cores, a d...

20250291756. GRAPHICS PROCESSOR ADDRESSABLE BARRIERS

Abstract: One embodiment provides a graphics processor comprising a base die including a plurality of chiplet sockets and a plurality of chiplets coupled with the plurality of chiplet sockets. At least one of the plurality of chiplets including a plurality of processing elements, a distributed shared memory c...