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Category:Kuo-Cheng CHIANG

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Kuo-Cheng CHIANG

Executive Summary

Kuo-Cheng CHIANG is an inventor who has filed 19 patents. Their primary areas of innovation include No explanation available (9 patents), No explanation available (8 patents), No explanation available (7 patents), and they have worked with companies such as TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (8 patents), Taiwan Semiconductor Manufacturing Company, Ltd. (8 patents), Taiwan Semiconductor Manufacturing Company Ltd. (2 patents). Their most frequent collaborators include (16 collaborations), (4 collaborations), (4 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

  • H10D84/038 (No explanation available): 9 patents
  • H10D64/017 (No explanation available): 8 patents
  • H10D30/6735 (No explanation available): 7 patents
  • H10D30/014 (No explanation available): 7 patents
  • H10D30/43 (No explanation available): 7 patents
  • H10D30/6757 (No explanation available): 7 patents
  • H10D62/121 (No explanation available): 7 patents
  • H01L29/42392 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 6 patents
  • H10D84/013 (No explanation available): 5 patents
  • H10D84/83 (No explanation available): 5 patents
  • H01L29/0673 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
  • H01L29/66439 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
  • H01L29/66545 ({using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate}): 5 patents
  • H01L29/775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
  • H01L29/78696 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
  • H10D84/0151 (No explanation available): 4 patents
  • H10D62/151 (No explanation available): 4 patents
  • H10D84/0147 (No explanation available): 3 patents
  • H10D84/834 (No explanation available): 3 patents
  • H01L27/088 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
  • H10D64/018 (No explanation available): 3 patents
  • H10D64/021 (No explanation available): 2 patents
  • H10D84/0135 (No explanation available): 2 patents
  • H01L21/76843 ({formed in openings in a dielectric}): 2 patents
  • H01L21/76871 ({Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers}): 2 patents
  • H10D84/0149 (No explanation available): 2 patents
  • H01L21/823437 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
  • H01L21/823481 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
  • H01L29/41733 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L21/823412 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
  • H01L21/823418 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
  • H01L29/0847 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H10D30/62 (No explanation available): 2 patents
  • H10D62/115 (No explanation available): 2 patents
  • H10D84/0167 (No explanation available): 2 patents
  • H10D30/6219 (No explanation available): 2 patents
  • H10D62/116 (No explanation available): 2 patents
  • H01L21/76885 ({By forming conductive members before deposition of protective insulating material, e.g. pillars, studs}): 1 patents
  • H01L23/528 ({Geometry or} layout of the interconnection structure {(): 1 patents
  • H10D84/0158 (No explanation available): 1 patents
  • H01L21/28518 (from a gas or vapour, e.g. condensation): 1 patents
  • H01L29/45 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/0665 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/66553 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 1 patents
  • H01L29/78651 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/42384 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/785 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2029/7858 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/535 (including internal interconnections, e.g. cross-under constructions {(internal lead connections): 1 patents
  • H01L21/76897 ({Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step (self-aligned silicidation on field effect transistors): 1 patents
  • H01L29/401 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/3192 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H10D30/031 (No explanation available): 1 patents
  • H01Q21/0043 ({Slotted waveguides (combination with horns): 1 patents
  • H01P3/16 (Dielectric waveguides, i.e. without a longitudinal conductor): 1 patents
  • H01Q1/3233 ({particular used as part of a sensor or in a security system, e.g. for automotive radar, navigation systems}): 1 patents
  • H01Q13/0233 ({Horns fed by a slotted waveguide array (biconical horns): 1 patents
  • H01L21/76802 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
  • H01L21/823468 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
  • H01L21/823475 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
  • H01L29/6656 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 1 patents
  • H10D84/0128 (No explanation available): 1 patents
  • H01L21/0337 ({characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment}): 1 patents
  • H01L21/28088 (Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups): 1 patents
  • H01L21/3086 ({characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment}): 1 patents
  • H10D30/0243 (No explanation available): 1 patents
  • H10D64/667 (No explanation available): 1 patents
  • H10D84/0172 (No explanation available): 1 patents
  • H10D84/0184 (No explanation available): 1 patents
  • H10D84/0188 (No explanation available): 1 patents
  • H10D84/0193 (No explanation available): 1 patents
  • H10D84/853 (No explanation available): 1 patents
  • H10D30/024 (No explanation available): 1 patents
  • H10D62/118 (No explanation available): 1 patents
  • H10D62/83 (No explanation available): 1 patents
  • H01L21/823807 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
  • H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H10D84/85 (No explanation available): 1 patents

Companies

List of Companies

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 8 patents
  • Taiwan Semiconductor Manufacturing Company, Ltd.: 8 patents
  • Taiwan Semiconductor Manufacturing Company Ltd.: 2 patents
  • Taiwan Semiconductor Manufacturing Company Limited: 1 patents

Collaborators

Subcategories

This category has the following 5 subcategories, out of 5 total.

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