Category:Hsien-Wei Chen

Hsien-Wei Chen

Executive Summary

Hsien-Wei Chen is an inventor who has filed 9 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (5 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), and they have worked with companies such as Taiwan Semiconductor Manufacturing Company, Ltd. (7 patents), Taiwan Semiconductor Manufacturing Company Limited (2 patents). Their most frequent collaborators include (5 collaborations), (4 collaborations), (4 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

• H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
• H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L24/73 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L25/0655 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L2224/32225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L2224/73204 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L2224/16227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L21/561 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/06 ({of a plurality of bonding areas}): 2 patents
• H01L23/49822 ({Multilayer substrates (multilayer metallisation on monolayer substrate): 2 patents
• H01L23/5383 ({Multilayer substrates (): 2 patents
• H01L25/105 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L25/50 ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 2 patents
• H01L21/565 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/3135 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/3114 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/49816 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
• H01L23/5389 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
• H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05008 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05022 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05099 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/12105 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/16145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/181 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/49503 (Lead-frames {or other flat leads (): 1 patents
• H01L21/76898 ({formed through a semiconductor substrate}): 1 patents
• H01L23/49827 ({Via connections through the substrates, e.g. pins going through the substrate, coaxial cables (): 1 patents
• H01L23/528 ({Geometry or} layout of the interconnection structure {(): 1 patents
• H01L21/4846 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 1 patents
• H01L24/13 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/14 ({of a plurality of bump connectors}): 1 patents
• H01L24/19 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/81 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/08146 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/16 (Fillings or auxiliary members in containers {or encapsulations}, e.g. centering rings (): 1 patents
• H01L21/50 (Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups): 1 patents
• H01L23/3107 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/367 (Cooling facilitated by shape of device {(): 1 patents
• H01L2224/16238 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/32245 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/73253 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/16235 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/16251 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L33/52 (Encapsulations): 1 patents
• G02B6/12004 (of the integrated circuit kind (electric integrated circuits): 1 patents
• G02B6/4206 (Coupling light guides with opto-electronic elements): 1 patents
• H01L25/167 (the devices being of types provided for in two or more different main groups of groups): 1 patents
• H01L31/0203 (Containers; Encapsulations {, e.g. encapsulation of photodiodes} (for photovoltaic devices): 1 patents
• H01L31/02325 (Optical elements or arrangements associated with the device (): 1 patents
• H01L31/18 (Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof): 1 patents
• H01L33/58 (Optical field-shaping elements): 1 patents
• H01L33/62 (Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls): 1 patents
• H01L2933/005 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2933/0058 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/562 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/3157 ({Partial encapsulation or coating (mask layer used as insulation layer): 1 patents
• H01L21/78 (with subsequent division of the substrate into plural individual devices (cutting to change the surface-physical characteristics or shape of semiconductor bodies): 1 patents
• H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 1 patents
• H01L2224/06519 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06524 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06541 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06586 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06589 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/6835 ({using temporarily an auxiliary support}): 1 patents
• H01L23/5381 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
• H01L24/96 ({the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting}): 1 patents
• H01L24/97 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/16235 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/96 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/97 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/3511 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10D88/00 (No explanation available): 1 patents
• H01L21/76816 ({Aspects relating to the layout of the pattern or to the size of vias or trenches (layout of the interconnections per se): 1 patents
• H01L21/76877 ({Thin films associated with contacts of capacitors}): 1 patents
• H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/09 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/33 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/02371 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/02372 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/02379 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/3128 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/49811 ({Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads (): 1 patents

Companies

List of Companies

• Taiwan Semiconductor Manufacturing Company, Ltd.: 7 patents
• Taiwan Semiconductor Manufacturing Company Limited: 2 patents

Collaborators

• Ming-Fa Chen (5 collaborations)
• Ying-Ju Chen (4 collaborations)
• Meng-Liang Lin (4 collaborations)
• Shin-Puu Jeng (4 collaborations)
• Jie Chen (3 collaborations)
• Sheng-An Kuo (1 collaborations)
• Ching-Jung Yang (1 collaborations)
• Fu Fan (1 collaborations)