SELECTIVELY MERGED GATES IN STACKED FETS

Abstract: semiconductor devices and methods of forming the same include a bottom transistor having a bottom gate. a top transistor has a top gate above the bottom gate and is separated from the bottom transistor by a dielectric layer. a conductive via extends through the top gate and the dielectric layer to contact the bottom transistor. a dielectric liner between the conductive via and the top gate electrically insulates the top gate from the conductive via.

Inventor(s): Shay Reboh, Albert M. Chu, Junli Wang, Ruilong Xie

CPC Classification: H10D84/856 (No explanation available)

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