METHOD OF CONTROLLING METAL GATE HEIGHT AND SELECTIVE SPACER FORMATION

Abstract: integrated circuit (ic) devices with non-planar transistors may be formed from a material stack having a sacrificial layer between one or more mask material layers and a top surface of a channel material. an ic device may include a non-planar transistor with a gate spacer layer having portions with a same or consistent composition, both over an upper surface of the channel material and under a lower surface of the channel material. the gate spacer layer may have a different composition than a gate endcap spacer layer.

Inventor(s): Shao Ming Koh, Sudipto Naskar, Matthew Prince, Vivek Thirtha, Marvin Paik

CPC Classification: H10D30/43 (No explanation available)

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