DIRECTED SELF ASSEMBLY-ENABLED BACK-SIDE CONTACT ARRAYS ALIGNED TO GATE ELECTRODES

Abstract: transistor structures between and coupled to front- and back-side interconnect layers may have precisely aligned arrays of contacts and dielectric structures over and under the transistor structures. transistor structures may have a gate electrode thickness under a channel region one-and-a-half or two times greater than a thickness between adjacent nanoribbons in the channel region. front- and back-side spacer layers with a same composition may have a discernible interface. contacts and dielectric structures on a back side may be formed using directed self-assembly of sacrificial materials aligned to gate electrodes revealed on a substrate back side.

Inventor(s): Ehren Mannebach, Shaun Mills, Joseph D’Silva, Mauro Kobrinsky, Umang Desai

CPC Classification: H01L23/528 ({Geometry or} layout of the interconnection structure {( takes precedence; algorithms )})

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