INTEGRATED CIRCUIT TESTING STRUCTURE FOR PAD BOND MISALIGNMENT DETECTION AND MEASUREMENT

Abstract: an integrated circuit (ic) package comprises a stack with first and second electronic devices respectively having a first array and a second array of rows and columns of pads bonded to each other. at least one testing structure comprises a first pattern of first pads of the first array, a second pattern of second pads of the second array, and at least four pad-pairs of one of the first pads adjacent to one of the second pads, wherein each pair has different pads than the other pairs. an aligned state of the first and second electronic devices exists wherein each pad-pair has a different offset length separating the first pad from the second pad, and wherein none of the first and second pads of the pairs are electrically connected.

Inventor(s): Jagat Shakya, Ankit Singh, Ethan Caughey, Joseph Parks

CPC Classification: G01R31/2896 ({Testing of IC packages; Test features related to IC packages (containers per se , encapsulations per se )})

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