OFFSET STAGGERED STACKED FIELD EFFECT TRANSISTOR (SFET) DEVICES

Abstract: embodiments are disclosed for a semiconductor structure. the semiconductor structure includes a standard logic cell having a top field effect transistor (fet) and a bottom fet. further, the top fet includes multiple top channels, additionally, the top channels are in contact with a first dielectric liner of a first gate cut region. further, the bottom fet includes multiple bottom channels. additionally, the bottom channels are in contact with a second dielectric liner of a second gate cut region. further, the top fet and the bottom fet share a gate. additionally, the top fet is disposed in an offset position with respect to the bottom fet.

Inventor(s): Ruilong Xie, Tao Li, Shay Reboh, Debarghya Sarkar, Chen Zhang

CPC Classification: H10D84/038 (No explanation available)

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