CHANNEL ISOLATION FOR A LOW-POWER SEMICONDUCTOR DEVICE

Abstract: a semiconductor chip with at least one low-power nanosheet gate-all-around field-effect transistor with a backside contact and a high-performance nanosheet gate-all-around field-effect transistor. the low-power gate-all-around field-effect transistor has a source/drain electrically isolated from at least a bottom nanosheet channel. the high-performance gate-all-around field-effect transistor with a source/drain contacting each of the plurality of nanosheet channels. the low-power nanosheet gate-all-around field semiconductor device includes a dielectric material electrically isolating at least the bottom channel from a backside contact and the source/drain. the high-performance nanosheet gate-all-around field-effect transistor includes a backside contact contacting at least the source/drain, the dielectric material, inner gate spacers, and a backside power rail. the backside contact of the low-power nanosheet gate-all-around field-effect transistor and the high-performance nanosheet gate-all-around field-effect transistor contacts a backside power rail connecting to a backside power delivery network.

Inventor(s): Min Gyu Sung, Tao Li, Ruilong Xie, Eric Miller

CPC Classification: H01L23/5286 ({Geometry or} layout of the interconnection structure {( takes precedence; algorithms )})

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