20250182839. Memory Parallel M (Micron Technology, .)

MEMORY WITH PARALLEL MAIN AND TEST INTERFACES

Abstract: methods, systems, and devices for memory with parallel main and test interfaces are described. a memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). for example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. the memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. by implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.

Inventor(s): James Brian Johnson, Kunal R. Parekh, Brent Keeth, Eiichi Nakano, Amy Rae Griffin

CPC Classification: G11C29/56004 (STATIC STORES (semiconductor memory devices ))

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