18814442. PARASITICS EXTRACTION BASED ON MULTIPLE MANUFACTURING PROCESS VARIATIONS (D2S, Inc.)
PARASITICS EXTRACTION BASED ON MULTIPLE MANUFACTURING PROCESS VARIATIONS
Organization Name
Inventor(s)
Donald Oriordan of Sunnyvale CA (US)
Akira Fujimura of Saratoga CA (US)
PARASITICS EXTRACTION BASED ON MULTIPLE MANUFACTURING PROCESS VARIATIONS
This abstract first appeared for US patent application 18814442 titled 'PARASITICS EXTRACTION BASED ON MULTIPLE MANUFACTURING PROCESS VARIATIONS
Original Abstract Submitted
Some embodiments provide a method for performing parasitic extraction for a layer of a design layout of an integrated circuit (IC). The design layout includes a set of conductive circuit components that traverse within a plane defined for the layer. The method identifies, for a particular conductive circuit component, multiple different three-dimensional (3-D) shapes that have different variations in a direction orthogonal to the plane based on different sets of manufacturing process conditions. The method uses the different 3-D shapes to compute a set of parasitic values for the particular conductive circuit component that express parasitic effects affecting the particular conductive circuit component in the IC.