18428623. BIT LINE STRUCTURE FOR MEMORY DEVICES (Taiwan Semiconductor Manufacturing Co., Ltd.)
BIT LINE STRUCTURE FOR MEMORY DEVICES
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Feng-Ming Chang of Hsinchu County TW
Jui-Lin Chen of Taipei City TW
BIT LINE STRUCTURE FOR MEMORY DEVICES
This abstract first appeared for US patent application 18428623 titled 'BIT LINE STRUCTURE FOR MEMORY DEVICES
Original Abstract Submitted
A semiconductor structure according to the present disclosure includes a first memory array in a first cache and a second memory array in a second cache. The first memory array includes a plurality of first memory cells arranged in M rows and N columns. The second memory array includes a plurality of second memory cells arranged in M rows and N columns. The semiconductor structure also includes a first bit line coupled to a number of N first memory cells in one of the M rows, and a second bit line coupled to a number of N second memory cells in one of the M rows. N is smaller than N and a width of the first bit line is smaller than a width of the second bit line.