18377672. DUAL SIDE STACKED TRANSISTOR (INTERNATIONAL BUSINESS MACHINES CORPORATION)

DUAL SIDE STACKED TRANSISTOR

Organization Name

INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor(s)

Ruilong Xie of Niskayuna NY US

Junli Wang of Slingerlands NY US

Kisik Choi of Watervliet NY US

Koichi Motoyama of Clifton Park NY US

Nicholas Anthony Lanzillo of Wynantskill NY US

Biswanath Senapati of Mechanicville NY US

Albert M. Chu of Nashua NH US

Brent A. Anderson of Jericho VT US

Chen Zhang of Santa Clara CA US

Tenko Yamashita of Schenectady NY US

DUAL SIDE STACKED TRANSISTOR

This abstract first appeared for US patent application 18377672 titled 'DUAL SIDE STACKED TRANSISTOR

Original Abstract Submitted

A semiconductor structure includes an upper-level CMOS transistor layer having a plurality of upper-level N-type and P-type field effect transistors; and a frontside interconnect layer above, and interconnected with, the upper-level transistor layer. The frontside interconnect layer includes frontside power rails and frontside signal wiring, and at least three frontside interconnect layer metal levels. A lower-level CMOS transistor layer has a plurality of lower-level N-type and P-type field effect transistors; and a backside interconnect layer below, and interconnected with, the lower-level transistor layer. The backside interconnect layer includes backside power rails and backside signal wiring and at least three backside interconnect layer metal levels. At a peripheral region of the structure, at least one conductive interconnection is provided between a third or higher of the at least three frontside interconnect layer metal levels and a third or lower of the at least three backside interconnect layer metal levels.