18374929. NBTI REDUCTION AND RELIABILITY IMPROVEMENT FOR SELECTIVE LAYOUTS (INTEL CORPORATION)
NBTI REDUCTION AND RELIABILITY IMPROVEMENT FOR SELECTIVE LAYOUTS
Organization Name
Inventor(s)
Rahul Pandey of Hillsboro OR US
Rahul Ramamurthy of Hillsboro OR US
Jubin Nathawat of Hillsboro OR US
Michael L. Hattendorf of Portland OR US
Anant H. Jahagirdar of Portland OR US
Steven R. Novak of Portland OR US
Paul A. Packan of Hillsboro OR US
David J. Towner of Portland OR US
NBTI REDUCTION AND RELIABILITY IMPROVEMENT FOR SELECTIVE LAYOUTS
This abstract first appeared for US patent application 18374929 titled 'NBTI REDUCTION AND RELIABILITY IMPROVEMENT FOR SELECTIVE LAYOUTS
Original Abstract Submitted
An integrated circuit structure comprises a fin extending from a substrate, the fin comprising source and drain regions, and a channel region between the source and drain regions. A multilayer high-k gate stack comprising a plurality of materials extends conformally over the fin over the channel region. A gate electrode is over and on a topmost material in the multilayer high-k gate stack. Fluorine is implanted in the substrate beneath the multilayer high-k gate stack or in the plurality of materials comprising the multilayer high-k gate stack.
- INTEL CORPORATION
- Rahul Pandey of Hillsboro OR US
- Yang Cao of Beaverton OR US
- Rahul Ramamurthy of Hillsboro OR US
- Jubin Nathawat of Hillsboro OR US
- Michael L. Hattendorf of Portland OR US
- Jae Hur of Hillsboro OR US
- Anant H. Jahagirdar of Portland OR US
- Steven R. Novak of Portland OR US
- Tao Chu of Portland OR US
- Yanbin Luo of Portland OR US
- Minwoo Jang of Portland OR US
- Paul A. Packan of Hillsboro OR US
- Owen Y. Loh of Portland OR US
- David J. Towner of Portland OR US
- H01L29/51
- H01L21/3115
- H01L29/40
- H01L29/78
- CPC H10D64/683
