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| − | '''Summary of the patent applications from Western Digital Technologies, Inc. on November 30th, 2023'''
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| − | Western Digital Technologies, Inc. has recently filed several patents related to various aspects of data storage devices and technologies. These patents cover areas such as semiconductor structures, digital signature verification, spin-orbit torque magnetic tunnel junction (SOT MTJ) devices, tape assembly implementation, disk coatings, emergency power-off procedures, motor control modes, lane selection based on thermal conditions, and lane detection and configuration.
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| − | Notable recent patent applications from Western Digital Technologies, Inc. include:
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| − | - A semiconductor structure with alternating layers of insulating and conductive materials, featuring stepped surfaces and a metal oxide etch stop layer.
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| − | - A method for verifying the authenticity of a digital signature using elliptic curve cryptography (ECC) and authenticating the use of a message based on this verification.
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| − | - An innovation aimed at improving the performance and stability of spin-orbit torque magnetic tunnel junction (SOT MTJ) devices by utilizing specific buffer and interlayer materials.
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| − | - A simplified and efficient design for tape assembly in magnetic recording devices, involving mounting reels with hubs and flanges or flangeless hubs.
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| − | - A disk for a magnetic recording apparatus with a substrate coated on both surfaces, where the maximum difference in thickness between the coating layers is determined by the square of the disk thickness.
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| − | - A data storage device with two read-write heads and two disks, each controlled by separate actuators, and an emergency power-off procedure that retracts and parks the actuators before braking the spindle motor.
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| − | - A data storage device with disks and a motor capable of operating in both PWM and linear modes, transitioning between the modes and compensating for a transition offset to move the disk heads to a target track.
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| − | - Methods and systems for lane selection based on thermal conditions, where the number of lanes used for communication with the data storage device is reduced to control the thermal state.
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| − | - Methods and systems for lane detection and configuration, automatically detecting the orientation of a cable connected to the data storage device and configuring the lane accordingly.
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| − | - A storage system that stores data in a primary block and a secondary block, with data and its copy stored in both blocks along with parity bits for error protection, and the primary block lacking a header to increase error protection for the data.
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| − | In summary, Western Digital Technologies, Inc. has recently filed patents covering a range of innovations in data storage devices and technologies, including semiconductor structures, digital signature verification, SOT MTJ devices, tape assembly, disk coatings, emergency power-off procedures, motor control modes, lane selection based on thermal conditions, lane detection and configuration, and storage system designs.
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| | ==Patent applications for Western Digital Technologies, Inc. on November 30th, 2023== | | ==Patent applications for Western Digital Technologies, Inc. on November 30th, 2023== |
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| | Feisheng Feng | | Feisheng Feng |
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| − | '''Brief explanation'''
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| − | The present invention is a coal-based solid waste transport and filling integrated machine mining system. It includes a filling hydraulic support and a coal winning machine.
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| − |
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| − | * The filling hydraulic support consists of a hydraulic top plate and a base.
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| − | * The hydraulic top plate has a hinged front top beam and a rear top beam.
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| − | * A front probe beam is attached to the front end of the front top beam, and a telescopic slide rod is connected to the rear end of the rear top beam.
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| − | * A double transport and single filling non-stop equipment is fixed on the telescopic slide rod.
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| − |
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| − | The invention aims to reduce the impact of groundwater pollution on mine production and mine ecology. It brings economic and environmental benefits to the mine and promotes safe and green coal mining.
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| − |
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| − | '''Abstract'''
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| − | The present invention provides a coal-based solid waste transport and filling integrated machine mining system, comprising a filling hydraulic support () and a coal winning machine (), said filling hydraulic support () comprises a hydraulic top plate and a base (), said hydraulic top plate comprises a hinged front top beam () and a rear top beam (), with a front probe beam () attached to front end of said front top beam () and a telescopic slide rod () connected to rear end of said rear top beam (), a double transport and single filling non-stop equipment is fixed on the telescopic slide rod (). The apparatus and method of the present invention weaken the impact of groundwater pollution on mine production and mine ecology, bring good economic and environmental benefits to the mine and promoting safe and green coal mining.
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| | ===Storage System and Method for Data Placement in Zoned Storage ([[US Patent Application 17860548. Storage System and Method for Data Placement in Zoned Storage simplified abstract|17860548]])=== | | ===Storage System and Method for Data Placement in Zoned Storage ([[US Patent Application 17860548. Storage System and Method for Data Placement in Zoned Storage simplified abstract|17860548]])=== |
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| | Rotem Sela | | Rotem Sela |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract of the patent application describes a storage system that uses larger memory blocks to store multiple zones.
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| − | * The storage system stores zones with similar properties in a given block.
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| − | * Storing zones with different properties in the same block can cause problems.
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| − | * The storage system obtains zone property information for each zone to ensure compatibility.
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| − | * Storing zones with similar properties in a block improves efficiency and organization.
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| − |
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| − | '''Abstract'''
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| − | A storage system uses blocks of memory that are sized larger than a size of a zone. This means that the storage system stores multiple zones in a given block. Storing zones with different one properties in a given block can be problematic, so the storage system obtains zone property information for each zone and stores zones with similar zone properties in a given block.
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| | | | |
| | ===Data Storage Device and Method for Device-Initiated Hibernation ([[US Patent Application 17752305. Data Storage Device and Method for Device-Initiated Hibernation simplified abstract|17752305]])=== | | ===Data Storage Device and Method for Device-Initiated Hibernation ([[US Patent Application 17752305. Data Storage Device and Method for Device-Initiated Hibernation simplified abstract|17752305]])=== |
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| | Judah Gamliel Hahn | | Judah Gamliel Hahn |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a data storage device and method for device-initiated hibernation.
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| − | * The data storage device includes a non-volatile memory and a controller.
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| − | * During the set-up phase of a hibernation process, the controller receives write commands from a host, which indicate the current state of the host's volatile memory.
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| − | * These write commands are stored in a queue and not executed immediately.
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| − | * The controller then receives a trigger from the host to start the execution phase of the hibernation process.
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| − | * In response to the trigger, the controller executes the stored write commands, saving the current state of the host's volatile memory in the non-volatile memory of the data storage device.
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| − | * This allows for efficient hibernation of the host system and quick resumption of operations when needed.
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| − | * The invention can be used alone or in combination with other embodiments.
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| − |
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| − | '''Abstract'''
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| − | A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
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| | ===Storage System and Method for Hybrid Mapping ([[US Patent Application 17752470. Storage System and Method for Hybrid Mapping simplified abstract|17752470]])=== | | ===Storage System and Method for Hybrid Mapping ([[US Patent Application 17752470. Storage System and Method for Hybrid Mapping simplified abstract|17752470]])=== |
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| | Ran Zamir | | Ran Zamir |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract of this patent application describes a storage system that has multiple memory mappings to translate data bits into different physical voltage levels in its non-volatile memory. The system allows a host to select a specific memory mapping based on the application or expected workload. The selected memory mapping is then used for memory access operations such as reading or writing data.
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| − |
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| − | * The storage system has multiple memory mappings to translate data bits into different physical voltage levels.
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| − | * The host can select a specific memory mapping based on the application or expected workload.
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| − | * The selected memory mapping is used for memory access operations.
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| − | * Memory access operations include reading or writing data.
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| − |
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| − | '''Abstract'''
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| − | A storage system supports several memory mappings that translate data bits into different physical voltage levels in its non-volatile memory. The storage system receives a selection of one of the memory mappings from a host, which makes the selection based on an application or expected workload of the host. The storage system uses the selected memory mapping for a memory access operation, such as a read operation or a write operation.
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| | ===DATA STORAGE DEVICE WITH MULTI-COMMANDS ([[US Patent Application 17825824. DATA STORAGE DEVICE WITH MULTI-COMMANDS simplified abstract|17825824]])=== | | ===DATA STORAGE DEVICE WITH MULTI-COMMANDS ([[US Patent Application 17825824. DATA STORAGE DEVICE WITH MULTI-COMMANDS simplified abstract|17825824]])=== |
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| | Dinesh Kumar Agarwal | | Dinesh Kumar Agarwal |
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| − | '''Brief explanation'''
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| − | The patent application discusses a method to improve the performance of a data storage device by reducing hardware and firmware overheads at the flash interface module (FIM).
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| − | * Constant fixed commands given to memory dies in a data storage device can cause performance issues due to the overheads associated with them.
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| − | * To avoid this impact, multiple fixed commands can be combined into individual multi-commands and provided to the memory dies.
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| − | * This use of multi-commands reduces the overheads at the FIM, improving the performance of the data storage device.
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| − | * By decreasing the saturation of the FIM, the overall performance of the data storage device is enhanced.
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| − |
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| − | '''Abstract'''
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| − | Providing constant fixed commands to memory dies within a data storage device may result in hardware and firmware overheads impacting the performance at a flash interface module (FIM) because the FIM has to handle both the constant fixed commands and the overheads associated with the constant fixed commands. To avoid the impact on performance at the FIM, multiple fixed commands may be combined into individual multi-commands that may be provided to the memory dies. The use of multi-commands reduces hardware and firmware overheads at the FIM relative to the constant fixed commands, which improves performance of the data storage device because the saturation of the FIM is decreased.
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| | ===Storage System and Method for Using a Queue Monitor in a Block Allocation Process ([[US Patent Application 17828285. Storage System and Method for Using a Queue Monitor in a Block Allocation Process simplified abstract|17828285]])=== | | ===Storage System and Method for Using a Queue Monitor in a Block Allocation Process ([[US Patent Application 17828285. Storage System and Method for Using a Queue Monitor in a Block Allocation Process simplified abstract|17828285]])=== |
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| | Kalpit Bordia | | Kalpit Bordia |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a storage system with a memory that can store multiple bits per cell or only one bit per cell.
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| − | * The storage system can choose to store only one bit per cell to improve performance.
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| − | * However, this can reduce the endurance of the memory.
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| − | * The storage system monitors a command queue to determine the required performance.
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| − | * Based on this information, the storage system decides whether it is worth sacrificing endurance for increased performance.
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| − |
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| − | '''Abstract'''
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| − | A storage system has a memory with a multi-level cell (MLC) block that can store multiple bits per cell or can be constrained to store only one bit per cell. Using the MLC block to store only one bit per cell can increase the performance of the storage system but can also reduce endurance of the MLC block. The storage system can monitor a command queue to determine the performance needed. With that information, the storage system can determine whether it is worth making the tradeoff of increasing performance at the cost of endurance.
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| | ===Storage System and Method for Early Command Cancelation ([[US Patent Application 17828489. Storage System and Method for Early Command Cancelation simplified abstract|17828489]])=== | | ===Storage System and Method for Early Command Cancelation ([[US Patent Application 17828489. Storage System and Method for Early Command Cancelation simplified abstract|17828489]])=== |
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| | Amir Segev | | Amir Segev |
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| − | '''Brief explanation'''
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| − | - The patent application describes a storage system that can cancel an in-progress read/write command.
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| − | - The storage system allows data associated with the command to continue being processed by a data path.
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| − | - However, before the data is transferred out of the data path, a controller determines that the command was cancelled.
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| − | - The controller prevents the data from being transferred out, while internally indicating that the transfer was complete.
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| − | - This approach provides a faster cancellation process compared to methods that try to stop the data from being processed by the data path.
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| − |
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| − | '''Abstract'''
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| − | A storage system receives an instruction to cancel an in-progress read/write command. The storage system allows data associated with the command to continue to be processed by a data path in the storage system even though the command was cancelled. However, before the data is actually transferred out of the data path, a controller determines that the command was cancelled and prevents the data from being transferred out, while internally indicating that the transfer was complete. This provides a faster cancellation process than methods that attempt to stop the data from being processed by the data path.
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| | ===Data Storage Device and Method for Storage-Class-Memory-Accelerated Boot Partition Optimization ([[US Patent Application 17752264. Data Storage Device and Method for Storage-Class-Memory-Accelerated Boot Partition Optimization simplified abstract|17752264]])=== | | ===Data Storage Device and Method for Storage-Class-Memory-Accelerated Boot Partition Optimization ([[US Patent Application 17752264. Data Storage Device and Method for Storage-Class-Memory-Accelerated Boot Partition Optimization simplified abstract|17752264]])=== |
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| | Judah Gamliel Hahn | | Judah Gamliel Hahn |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a data storage device with two memory units and a controller.
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| − |
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| − | * The first memory has faster access time than the second memory.
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| − | * The controller stores a code called host-initialization code in the first memory.
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| − | * A copy of the host-initialization code is also stored in the second memory.
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| − | * The controller determines that the copy of the code in the second memory should be designated as the main version.
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| − | * The controller then relocates the copy of the code to the first memory, making it the main version.
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| − | * This main version of the code is accessed to boot-up the host.
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| − | * The patent application mentions that there can be other embodiments and combinations of these features.
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| − |
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| − | '''Abstract'''
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| − | A data storage device comprises a first memory, a second memory, and a controller. The first memory has a faster access time than the second memory. The controller is configured to store host-initialization code in the first memory, store a copy of the host-initialization code in the second memory, determine that the copy of the host-initialization code should be designated as the main version of the host-initialization code, and relocate the copy of the host-initialization code to the first memory, which makes the copy of the host-initialization code the main version of the host-initialization code that is accessed to boot-up the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
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| | ===Variable Length ECC Code According To Data Entropy In NVMe Key Value Pair Devices ([[US Patent Application 17827193. Variable Length ECC Code According To Data Entropy In NVMe Key Value Pair Devices simplified abstract|17827193]])=== | | ===Variable Length ECC Code According To Data Entropy In NVMe Key Value Pair Devices ([[US Patent Application 17827193. Variable Length ECC Code According To Data Entropy In NVMe Key Value Pair Devices simplified abstract|17827193]])=== |
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| | David AVRAHAM | | David AVRAHAM |
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| − |
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| − | '''Brief explanation'''
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| − | - The patent application describes a data storage device that includes a memory device and a controller.
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| − | - The controller is responsible for receiving key value (KV) pair data and determining the entropy value of the received data.
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| − | - Based on the determined entropy value, the controller selects an error correction code (ECC) code rate.
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| − | - The KV pair data consists of a key and a value, and the controller encodes this data using the selected ECC code rate.
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| − | - Additionally, the controller aggregates a portion of another KV pair data with the original data and encodes the aggregated data using the selected ECC code rate.
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| − | - The encoded KV pair data is then programmed to a codeword (CW) in the memory device.
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| − | - The purpose of this innovation is to improve the efficiency and reliability of data storage by using an appropriate ECC code rate based on the entropy value of the data.
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| − |
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| − | '''Abstract'''
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| − | A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data, determine an entropy value of the received KV pair data, select an error correction code (ECC) code rate based on the determined entropy value, and program the KV pair data to a codeword (CW). The KV pair data includes a key and a value. The programming includes encoding the KV pair data using the selected ECC code rate. The controller is further configured to aggregate a portion of another KV pair data and the KV pair data and program the aggregated KV pair data to the CW using a selected ECC code rate.
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| | ===PROACTIVE LOSS NOTIFICATION AND HANDLING IN DATA STORAGE DEVICES ([[US Patent Application 17752771. PROACTIVE LOSS NOTIFICATION AND HANDLING IN DATA STORAGE DEVICES simplified abstract|17752771]])=== | | ===PROACTIVE LOSS NOTIFICATION AND HANDLING IN DATA STORAGE DEVICES ([[US Patent Application 17752771. PROACTIVE LOSS NOTIFICATION AND HANDLING IN DATA STORAGE DEVICES simplified abstract|17752771]])=== |
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| | Bhavya Krishna | | Bhavya Krishna |
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| − | '''Brief explanation'''
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| − | The patent application describes devices, systems, and methods for proactive data loss notification and handling in data storage devices.
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| − | * The data storage device includes a memory and a controller.
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| − | * The controller has a processor and controller memory.
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| − | * The controller memory stores instructions for the controller to perform certain actions.
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| − | * During an internal data movement process, if an uncorrectable error correction code (UECC) is detected, the controller modifies a metadata field associated with the corresponding logical block address.
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| − | * The host device is informed about the UECC.
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| − | * The controller then determines whether data stored in adjacent regions to the logical block address is lost.
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| − | * This technology aims to proactively notify and handle data loss situations in data storage devices.
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| − |
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| − | '''Abstract'''
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| − | Devices, systems, and methods with proactive data loss notification and handling. A data storage device includes a memory and a controller. The controller includes a processor and controller memory. The controller memory stores a set of instructions that, when executed by the processor, instruct the controller to: detect an uncorrectable error correction code (UECC) during an internal data movement process of the storage device memory, modify a metadata field associated with a logical block address corresponding to the UECC, inform a host device about the UECC, and determine whether data stored in at least one adjacent region to the logical block address is lost.
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| | ===Efficient Logical to Physical Mapping Updates ([[US Patent Application 18316664. Efficient Logical to Physical Mapping Updates simplified abstract|18316664]])=== | | ===Efficient Logical to Physical Mapping Updates ([[US Patent Application 18316664. Efficient Logical to Physical Mapping Updates simplified abstract|18316664]])=== |
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| | Dinesh Kumar Agarwal | | Dinesh Kumar Agarwal |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a method for efficiently updating logical mappings within control table sets in storage devices or systems.
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| − | * Control table sets group logical mappings that correspond to the locations of data requested by a host-computing device and the physical locations of the data within the memory array.
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| − | * As data is written and erased, these mappings need to be updated within the control table set.
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| − | * Typically, changes to these mappings are stored and updated in both a cache memory and a control table update list.
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| − | * The invention proposes tracking and marking control table sets as dirty or having undergone multiple changes.
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| − | * This allows additional updates to be stored and updated only in the cache memory, bypassing the second control table change list.
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| − | * By utilizing only one method of updating control table sets, processing overhead is reduced and read or write activities are more efficiently performed.
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| − |
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| − | '''Abstract'''
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| − | Various devices, such as storage devices or systems are configured to efficiently process and update logical mappings within control table sets. Control table sets are often groupings of logical mapping corresponding to the logical locations of data requested by a host-computing device and the physical locations of the data within the memory array. As data is written and erased, these mappings must be updated within the control table set. Received changes to these mappings are typically stored and updated in two locations: a cache memory and a control table update list. By tracking and marking various control table sets as dirty or having undergone multiple changes, additional received updates can be stored and updated in only the cache memory, bypassing the second control table change list. By only utilizing one method of updating control table sets, processing overhead is reduced and various read or write activities are more efficiently done.
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| | ===Storage System and Method for Avoiding Header to Improve Parity ([[US Patent Application 17824066. Storage System and Method for Avoiding Header to Improve Parity simplified abstract|17824066]])=== | | ===Storage System and Method for Avoiding Header to Improve Parity ([[US Patent Application 17824066. Storage System and Method for Avoiding Header to Improve Parity simplified abstract|17824066]])=== |
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| | Arunkumar Mani | | Arunkumar Mani |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a storage system that stores data in a primary block and a secondary block.
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| − | * Data and its copy are stored in both blocks, along with parity bits for error protection.
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| − | * The secondary block also contains a header with logical block information.
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| − | * The primary block does not have a header, allowing for more parity bits to be stored with the data.
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| − | * This increases the error protection for the data in the primary block and reduces reliance on the secondary block.
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| − |
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| − | '''Abstract'''
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| − | A storage system stores data in a primary block and a copy of the data in a secondary block. Parity bits are stored with the data and the copy of the data. A header with logical block information is stored with the copy of the data in the secondary block. The data in the primary block is not stored with a header, which allows more parity bits to be stored with the data in the primary block. This provides more robust error protection for the data stored in the primary block and reduces the need to rely upon the copy of the data in the secondary block.
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| | ===Data Storage Device and Method for Lane Detection and Configuration ([[US Patent Application 17828334. Data Storage Device and Method for Lane Detection and Configuration simplified abstract|17828334]])=== | | ===Data Storage Device and Method for Lane Detection and Configuration ([[US Patent Application 17828334. Data Storage Device and Method for Lane Detection and Configuration simplified abstract|17828334]])=== |
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| | Anil Kumar Kolar Narayanappa | | Anil Kumar Kolar Narayanappa |
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| − |
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| − | '''Brief explanation'''
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| − | - The patent application describes a data storage device and method for lane detection and configuration.
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| − | - The device includes a memory, interface, and controller.
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| − | - The controller is able to detect the orientation of a cable connected to the interface.
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| − | - It can determine if the cable is in a first or second orientation based on the channel configuration signal it receives.
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| − | - If the cable does not provide either signal, the controller will use a default lane configuration to communicate with the host.
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| − | - The invention allows for automatic detection and configuration of the cable orientation.
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| − | - This ensures proper communication between the data storage device and the host.
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| − | - The invention can be used alone or in combination with other embodiments.
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| − |
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| − | '''Abstract'''
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| − | A data storage device and method for lane detection and configuration are provided. In one embodiment, a data storage device is provided comprising a memory, an interface, and a controller. The controller is configured to detect whether a cable coupled with the interface is providing a first channel configuration signal that indicates that the cable is in a first cable orientation or a second channel configuration signal that indicates that the cable is in a second cable orientation. In response to detecting that the cable is not providing either the first or the second channel configuration signal, the controller uses a default lane configuration to communicate with the host via the cable. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
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| | ===Data Storage Device and Method for Lane Selection Based on Thermal Conditions ([[US Patent Application 17828368. Data Storage Device and Method for Lane Selection Based on Thermal Conditions simplified abstract|17828368]])=== | | ===Data Storage Device and Method for Lane Selection Based on Thermal Conditions ([[US Patent Application 17828368. Data Storage Device and Method for Lane Selection Based on Thermal Conditions simplified abstract|17828368]])=== |
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| | Ramanathan Muthiah | | Ramanathan Muthiah |
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| − |
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| − | '''Brief explanation'''
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| − | - The patent application describes a data storage device and method for lane selection based on thermal conditions.
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| − | - The device includes a memory and a controller.
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| − | - The controller is designed to identify when action is required to control the thermal state of the data storage device.
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| − | - When action is needed, the controller sends a request to the host to reduce the number of lanes used for communication with the data storage device.
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| − | - Reducing the number of lanes helps to decrease the amount of heat generated by the data storage device.
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| − | - The invention can be used alone or in combination with other embodiments.
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| − |
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| − | '''Abstract'''
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| − | A data storage device and method for lane selection based on thermal conditions are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to determine that action is needed to control a thermal state of the data storage device; and in response to determining that action is needed to control the thermal state of the data storage device, send a request to a host to reduce a number of lanes the host uses to communicate with the data storage device, wherein reducing the number of lanes reduces an amount of heat generated by the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
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| | ===VCM PWM TO LINEAR MODE TRANSITION OFFSET OPTIMIZATION TO IMPROVE PES ([[US Patent Application 18446612. VCM PWM TO LINEAR MODE TRANSITION OFFSET OPTIMIZATION TO IMPROVE PES simplified abstract|18446612]])=== | | ===VCM PWM TO LINEAR MODE TRANSITION OFFSET OPTIMIZATION TO IMPROVE PES ([[US Patent Application 18446612. VCM PWM TO LINEAR MODE TRANSITION OFFSET OPTIMIZATION TO IMPROVE PES simplified abstract|18446612]])=== |
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| | Jaesoo Byoun | | Jaesoo Byoun |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract describes a data storage device with disks, a motor, and processing devices.
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| − | * The device has disks and a motor with disk heads that can operate in a PWM mode and a linear mode.
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| − | * The processing devices control the motor to move the disk heads to a target track.
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| − | * The motor transitions from PWM mode to linear mode, compensating for a transition offset.
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| − | * The motor then moves the disk heads to the target track in the linear mode for a specific time.
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| − |
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| − | '''Abstract'''
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| − | Various illustrative aspects are directed to a data storage device comprising one or more disks, an actuator arm assembly comprising one or more disk heads and a voice coil motor (VCM), the VCM configured to operate in a PWM mode and a linear mode, and one or more processing devices configured to: seek the VCM towards a target track in the PWM mode; transition the VCM from the PWM mode to the linear mode, wherein the transitioning comprises switching an offset compensation value from a first offset compensation value to a second compensation offset value to compensate for a transition offset induced while transitioning the VCM from the PWM to the linear mode, wherein the first and the second offset compensation values correspond to the PWM and linear modes, respectively, and seek the VCM towards the target track in the linear mode for a linear mode time.
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| | ===DATA STORAGE DEVICE HAVING DUAL ACTUATORS AND METHOD FOR EMERGENCY POWER OFF RETRACT (EPOR) OF DUAL ACTUATORS ([[US Patent Application 18446637. DATA STORAGE DEVICE HAVING DUAL ACTUATORS AND METHOD FOR EMERGENCY POWER OFF RETRACT (EPOR) OF DUAL ACTUATORS simplified abstract|18446637]])=== | | ===DATA STORAGE DEVICE HAVING DUAL ACTUATORS AND METHOD FOR EMERGENCY POWER OFF RETRACT (EPOR) OF DUAL ACTUATORS ([[US Patent Application 18446637. DATA STORAGE DEVICE HAVING DUAL ACTUATORS AND METHOD FOR EMERGENCY POWER OFF RETRACT (EPOR) OF DUAL ACTUATORS simplified abstract|18446637]])=== |
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| | Brian Johnson | | Brian Johnson |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a data storage device that includes two read-write heads and two disks, each controlled by separate actuators.
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| − | * The device also includes a spindle motor that rotates the disks.
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| − | * In the event of an emergency power off (EPO), a processing device retracts and parks the actuators using a generated internal supply voltage.
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| − | * The processing device also brakes the spindle motor, but only after both actuators have been retracted and parked.
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| − |
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| − | '''Abstract'''
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| − | A data storage device comprises a lead actuator that actuates a first read-write head over a first disk and a support actuator that actuates a second read-write head over a second disk. A spindle motor rotates the first and second disks. In response to an emergency power off (EPO) event, a processing device retracts and parks the actuators using an internal supply voltage generated from a back electromotive force (BEMF) voltage of the spindle motor, and brakes the spindle motor. The spindle motor is not braked until both the lead and support actuators have been retracted and parked.
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| | | | |
| | ===MAGNETIC RECORDING APPARATUS COMPRISING DISK WITH REDUCED THICKNESS AND REDUCED DISK FLATNESS ([[US Patent Application 18233497. MAGNETIC RECORDING APPARATUS COMPRISING DISK WITH REDUCED THICKNESS AND REDUCED DISK FLATNESS simplified abstract|18233497]])=== | | ===MAGNETIC RECORDING APPARATUS COMPRISING DISK WITH REDUCED THICKNESS AND REDUCED DISK FLATNESS ([[US Patent Application 18233497. MAGNETIC RECORDING APPARATUS COMPRISING DISK WITH REDUCED THICKNESS AND REDUCED DISK FLATNESS simplified abstract|18233497]])=== |
| Line 339: |
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| | Shoji Suzuki | | Shoji Suzuki |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a disk for a magnetic recording apparatus.
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| − | * The disk has a substrate with a first surface and a second surface, and it has a certain thickness.
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| − | * The first surface of the substrate is coated with a first coating layer, which also has a certain thickness.
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| − | * The second surface of the substrate is coated with a second coating layer, which also has a certain thickness.
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| − | * The overall thickness of the disk includes the thickness of the substrate.
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| − | * The maximum difference in thickness between the first coating layer and the second coating layer is determined by the square of the disk thickness.
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| − |
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| − | '''Abstract'''
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| − | A disk for a magnetic recording apparatus. The disk includes a substrate comprising a first surface and a second surface, wherein the substrate has a substrate thickness. The disk includes a first coating layer disposed over the first surface of the substrate, wherein the first coating layer has a first coating layer thickness. The disk includes a second coating layer disposed over the second surface of the substrate, wherein the second coating layer has a second coating layer thickness. The disk has a disk thickness, wherein the disk thickness includes the substrate thickness. The maximum thickness difference between the first coating layer thickness and the second coating layer thickness is a function of the square of the disk thickness.
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| | | | |
| | ===Tape Assemblies Having Flangeless Reel Configurations and Single Flange Reel Configurations For Magnetic Recording Devices ([[US Patent Application 17824745. Tape Assemblies Having Flangeless Reel Configurations and Single Flange Reel Configurations For Magnetic Recording Devices simplified abstract|17824745]])=== | | ===Tape Assemblies Having Flangeless Reel Configurations and Single Flange Reel Configurations For Magnetic Recording Devices ([[US Patent Application 17824745. Tape Assemblies Having Flangeless Reel Configurations and Single Flange Reel Configurations For Magnetic Recording Devices simplified abstract|17824745]])=== |
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| | Erhard SCHRECK | | Erhard SCHRECK |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract describes a tape assembly implementation for magnetic recording devices, specifically tape embedded drives (TEDs).
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| − | * The implementation involves mounting a first reel and a second reel at stationary positions.
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| − | * The first and/or second reel includes a hub mounted to a spindle and a single flange extending relative to the hub.
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| − | * Alternatively, the first and/or second reel may have a flangeless hub mounted to a spindle.
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| − | * The purpose of this implementation is to provide a simplified and efficient design for tape assembly in magnetic recording devices.
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| − |
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| − | '''Abstract'''
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| − | The present disclosure generally relate to tape assembly implementations for magnetic recording devices, such as tape embedded drives (TEDs). In one or more embodiments, a first reel and a second reel are mounted at stationary positions. One or more of the first reel and/or the second reel includes a hub mounted to a spindle, and a single flange extending relative to the hub. In one or more embodiments, one or more of a first reel and/or a second reel each includes a flangeless hub mounted to a spindle.
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| | | | |
| | ===Buffer Layers And Interlayers That Promote BiSbx (012) Alloy Orientation For SOT And MRAM Devices ([[US Patent Application 18232256. Buffer Layers And Interlayers That Promote BiSbx (012) Alloy Orientation For SOT And MRAM Devices simplified abstract|18232256]])=== | | ===Buffer Layers And Interlayers That Promote BiSbx (012) Alloy Orientation For SOT And MRAM Devices ([[US Patent Application 18232256. Buffer Layers And Interlayers That Promote BiSbx (012) Alloy Orientation For SOT And MRAM Devices simplified abstract|18232256]])=== |
| Line 376: |
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| | Quang LE | | Quang LE |
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| − |
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| − | '''Brief explanation'''
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| − | - The patent application is about spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices.
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| − | - These devices consist of a buffer layer, a bismuth antimony (BiSb) layer with a (012) orientation, and an interlayer.
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| − | - The buffer layer and interlayer can be single layers or multilayers of different materials.
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| − | - The buffer layer and interlayer are made of materials that prevent antimony (Sb) migration within the BiSb layer.
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| − | - They also enhance the uniformity of the BiSb layer and promote the desired (012) orientation.
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| − | - The innovation aims to improve the performance and stability of SOT MTJ devices.
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| − |
| |
| − | '''Abstract'''
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| − | The present disclosure generally relate to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a buffer layer, a bismuth antimony (BiSb) layer having a (012) orientation disposed on the buffer layer, and an interlayer disposed on the BiSb layer. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer each comprise at least one of a covalently bonded amorphous material, a tetragonal (001) material, a tetragonal (110) material, a body-centered cubic (bcc) (100) material, a face-centered cubic (fcc) (100) material, a textured bcc (100) material, a textured fcc (100) material, a textured (100) material, or an amorphous metallic material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the BiSb layer and enhance uniformity of the BiSb layer while further promoting the (012) orientation of the BiSb layer.
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| | | | |
| | ===SYSTEMS AND METHODS OF IMPROVED MODULAR INVERSION WITH DIGITAL SIGNATURES ([[US Patent Application 17827692. SYSTEMS AND METHODS OF IMPROVED MODULAR INVERSION WITH DIGITAL SIGNATURES simplified abstract|17827692]])=== | | ===SYSTEMS AND METHODS OF IMPROVED MODULAR INVERSION WITH DIGITAL SIGNATURES ([[US Patent Application 17827692. SYSTEMS AND METHODS OF IMPROVED MODULAR INVERSION WITH DIGITAL SIGNATURES simplified abstract|17827692]])=== |
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| | Ishai Ilani | | Ishai Ilani |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a method for verifying the authenticity of a digital signature using elliptic curve cryptography (ECC) and authenticating the use of a message based on this verification.
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| − |
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| − | * The method involves receiving a message and a digital signature associated with a signing party.
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| − | * The authenticity of the digital signature is verified using ECC.
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| − | * The verification process includes computing modular inverses, which involves identifying two integers and performing an iterative process.
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| − | * The iterative process initializes two integers with a pre-defined number of most significant bits from the original integers and computes a quotient and remainder.
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| − | * A resultant inverse value is determined using the quotient obtained from the iterative process.
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| − | * The authenticity of the digital signature is confirmed based on the resultant inverse value.
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| − |
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| − | Overall, the patent application presents a method for securely verifying digital signatures and ensuring the authenticity of messages using elliptic curve cryptography and modular inverse computations.
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| − |
| |
| − | '''Abstract'''
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| − | A method includes receiving a message and a digital signature associated with a signing party and the message, verifying authenticity of the digital signature using elliptic curve cryptography (ECC), and authenticating use of the message based, at least in part, on the confirmed authenticity of the digital signature. The verifying includes one or more computations involving computing modular inverses. Computing modular inverses includes identifying first and second integer of a modular inverse operation, performing a first iterative process that, at each iteration: (i) initializes a third integer with a pre-defined number of most significant bits of the first integer and a fourth integer with the pre-defined number of most significant bits of the second integer and (ii) computes a quotient and a remainder, determining a resultant inverse value using the quotient; and confirming the authenticity of the digital signature based, at least in part, on the resultant inverse value.
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| | | | |
| | ===THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A METAL OXIDE ETCH STOP LAYER AND METHODS FOR FORMING THE SAME ([[US Patent Application 18233697. THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A METAL OXIDE ETCH STOP LAYER AND METHODS FOR FORMING THE SAME simplified abstract|18233697]])=== | | ===THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A METAL OXIDE ETCH STOP LAYER AND METHODS FOR FORMING THE SAME ([[US Patent Application 18233697. THREE-DIMENSIONAL MEMORY DEVICE INCLUDING A METAL OXIDE ETCH STOP LAYER AND METHODS FOR FORMING THE SAME simplified abstract|18233697]])=== |
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| | | | |
| | Mitsuhiro Togo | | Mitsuhiro Togo |
| − |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a semiconductor structure that includes alternating layers of insulating and conductive materials. These layers have stepped surfaces.
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| − | * The semiconductor structure includes alternating layers of insulating and conductive materials.
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| − | * The layers have stepped surfaces.
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| − | * A metal oxide etch stop layer is present on the stepped surfaces.
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| − | * A dielectric material portion is present on the etch stop layer and the stepped surfaces.
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| − | * A memory opening extends vertically through the alternating layers.
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| − | * A memory fill structure is located in the memory opening and contains a memory film and a vertical semiconductor channel.
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| − | * An electrically conductive layer contact via structure extends vertically through the dielectric material portion and the etch stop layer.
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| − | * The via structure contacts one of the conductive layers.
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| − |
| |
| − | '''Abstract'''
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| − | A semiconductor structure includes an alternating stack of first insulating layers and first electrically conductive layers, the first alternating stack having first stepped surfaces, at least one first metal oxide etch stop layer overlying and contacting the first stepped surfaces, a first stepped dielectric material portion overlying the at least one first metal oxide etch stop layer and the first stepped surfaces, a memory opening vertically extending through the first alternating stack, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, and an electrically conductive layer contact via structure vertically extending through the first stepped dielectric material portion and the at least one first metal oxide etch stop layer, and contacting a respective one of the first electrically conductive layers.
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